M. C. Bhuvaneswari

According to our database1, M. C. Bhuvaneswari authored at least 6 papers between 2009 and 2013.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of six.

Timeline

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Bibliography

2013
Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits.
Int. J. Comput. Appl. Technol., 2013

2012
A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths.
VLSI Design, 2012

Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm.
VLSI Design, 2012

Task allocation in distributed computing systems using adaptive particle swarm optimisation.
Int. J. Comput. Appl. Technol., 2012

2011
A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2009
Efficient multi-objective genetic algorithm for hardware-software partitioning in embedded system design: ENGA.
Int. J. Comput. Appl. Technol., 2009


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