M. Bhaskar Sherigar

According to our database1, M. Bhaskar Sherigar authored at least 1 paper in 1998.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

1998
A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGA.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998


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