M. Balakrishnan

Commun. ACM, 2022

Beacon Placement and Signal Strength Estimation to Improve Localization Coverage and Accuracy.

[BibT_eX]

[DOI]

Vikas Upadhyay

Kashi Roy

Proceedings of the 12th IEEE International Conference on Indoor Positioning and Indoor Navigation, 2022

EXPRESS: CNN EXecution Time PREdiction for DPU DeSign Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2022

2021

Performance-Energy Trade-off in Modern CMPs.

[BibT_eX]

[DOI]

Solomon Abera

ACM Trans. Archit. Code Optim., 2021

Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2021

VmAP: A Fair Metric for Video Object Detection.

[BibT_eX]

[DOI]

Proceedings of the MM '21: ACM Multimedia Conference, Virtual Event, China, October 20, 2021

EnergyNN: Energy Estimation for Neural Network Inference Tasks on DPU.

[BibT_eX]

[DOI]

Shikha Goel

Rijurekha Sen

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

ASSISTECH: An Accidental Journey into Assistive Technology.

[BibT_eX]

[DOI]

Proceedings of the A Journey of Embedded and Cyber-Physical Systems, 2021

2020

INFER: INterFerence-aware Estimation of Runtime for Concurrent CNN Execution on DPUs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2020

A Genetic Algorithm Based Medical Image Watermarking for Improving Robustness and Fidelity in Wavelet Domain.

[BibT_eX]

[DOI]

Balasamy Krishnasamy

Arockia Christopher

Proceedings of the Intelligent Data Engineering and Analytics, 2020

2019

Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

MAVI: Mobility Assistant for Visually Impaired with Optional Use of Local and Cloud Resources.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Majority Logic: Prime Implicants and n-Input Majority Term Equivalence.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

ML Guided Energy-Performance Trade-Off Estimation For Uncore Frequency Scaling.

[BibT_eX]

[DOI]

Solomon Abera Bekele

Proceedings of the 2019 Spring Simulation Conference, 2019

Evaluating the Use of Variable Height in Tactile Graphics.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE World Haptics Conference, 2019

Multi-sensor Energy Efficient Obstacle Detection.

[BibT_eX]

[DOI]

Anupam Sobti

Chetan Arora

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

GRanDE: Graphical Representation and Design Space Exploration of Embedded Systems.

[BibT_eX]

[DOI]

Rajesh Kedia

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

A case for design space exploration of context-aware adaptive embedded systems: work-in-progress.

[BibT_eX]

[DOI]

Rajesh Kedia

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

2018

Task Assignment Algorithms for Multicore Platforms with Process Variations.

[BibT_eX]

[DOI]

J. Low Power Electron., 2018

Object Detection in Real-Time Systems: Going Beyond Precision.

[BibT_eX]

[DOI]

Anupam Sobti

Chetan Arora

Suman Adhepalli Muralikrishnan

Proceedings of the 2018 IEEE Winter Conference on Applications of Computer Vision, 2018

FPGA-Based Controllers for Compact Low Power Refreshable Braille Display.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Performance-Energy Trade-off in CMPs with Per-Core DVFS.

[BibT_eX]

[DOI]

Solomon Abera

Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017

Hardware acceleration of de novo genome assembly.

[BibT_eX]

[DOI]

Dominique Lavenier

Int. J. Embed. Syst., 2017

Optimal mapping of program overlays onto many-core platforms with limited memory capacity.

[BibT_eX]

[DOI]

Kiyoung Choi

Des. Autom. Embed. Syst., 2017

MAVI: An Embedded Device to Assist Mobility of Visually Impaired.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

PLSS: A Scheduler for Multi-core Embedded Systems.

[BibT_eX]

[DOI]

Solomon Abera

Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016

Leakage Power Aware Task Assignment Algorithms for Multicore Platforms.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015

Configurable Architectures for Multi-Mode Floating Point Adders.

[BibT_eX]

[DOI]

Manish Kumar Jaiswal

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Improving Map-Reduce for GPUs with cache.

[BibT_eX]

[DOI]

Arun Parakh

Int. J. High Perform. Syst. Archit., 2015

Super Edge Magic Graceful Labeling of Generalized Petersen Graphs.

[BibT_eX]

[DOI]

S. Kavitha

Electron. Notes Discret. Math., 2015

Vertex in-magic arc labelings of digraphs.

[BibT_eX]

[DOI]

S. Arumugam

Electron. Notes Discret. Math., 2015

E-Super Vertex In-Magic Total Labelings of Digraphs.

[BibT_eX]

[DOI]

S. Arumugam

Electron. Notes Discret. Math., 2015

Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014

Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Super edge magic graceful graphs.

[BibT_eX]

[DOI]

Inf. Sci., 2014

Series Expansion based Efficient Architectures for Double Precision Floating Point Division.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2014

Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Edutactile - A Tool for Rapid Generation of Accurate Guideline-Compliant Tactile Graphics for Science and Mathematics.

[BibT_eX]

[DOI]

Proceedings of the Computers Helping People with Special Needs, 2014

Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

LightSim: A leakage aware ultrafast temperature simulator.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Amdahl's law in the era of process variation.

[BibT_eX]

[DOI]

Geetika Malhotra

Int. J. High Perform. Syst. Archit., 2013

Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

FAssem: FPGA Based Acceleration of De Novo Genome Assembly.

[BibT_eX]

[DOI]

Dominique Lavenier

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

A path-guided audio based indoor navigation system for persons with visual impairment.

[BibT_eX]

[DOI]

Proceedings of the 15th International ACM SIGACCESS Conference on Computers and Accessibility, 2013

2012

Measures and Countermeasures for Null Frequency Jamming of On-Demand Routing Protocols in Wireless Ad Hoc Networks.

[BibT_eX]

[DOI]

Hong Huang

Rafael Asorey-Cacheda

Satyajayant Misra

Sandeep Pawar

Yousef Jaradat

IEEE Trans. Wirel. Commun., 2012

System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

E-super vertex magic labelings of graphs.

[BibT_eX]

[DOI]

Discret. Appl. Math., 2012

Performance Estimation of GPUs with Cache.

[BibT_eX]

[DOI]

Arun Parakh

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Power Consumption in Multi-core Processors.

[BibT_eX]

[DOI]

Proceedings of the Contemporary Computing - 5th International Conference, 2012

2011

Compressing Cache State for Postsilicon Processor Debug.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2011

Architecture and tools for programmable QCA.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010

Clocking-Based Coplanar Wire Crossing Scheme for QCA.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Enhancing post-silicon processor debug with Incremental Cache state Dumping.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A tiled programmable fabric using QCA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

2009

Integrated energy analysis of error correcting codes and modulation for energy efficient wireless sensor nodes.

[BibT_eX]

[DOI]

IEEE Trans. Wirel. Commun., 2009

A Framework for Energy-Consumption-Based Design Space Exploration for Wireless Sensor Nodes.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An experimental validation of system level design space exploration methodology for energy efficient sensor nodes.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Cache aware compression for processor debug support.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors.

[BibT_eX]

[DOI]

Aryabartta Sahu

Proceedings of the Design, Automation and Test in Europe, 2009

Online cache state dumping for processor debug.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2007

Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.

[BibT_eX]

[DOI]

Anup Gangwar

ACM Trans. Design Autom. Electr. Syst., 2007

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2007

Yield Prediction Through Feed Forward Neural Network Approach for Direct Seeded Rice (Oryza sativa) in Bay Islands.

[BibT_eX]

Proceedings of the 3rd Indian International Conference on Artificial Intelligence, 2007

A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures.

[BibT_eX]

[DOI]

Ashutosh Pal

Proceedings of the FPL 2007, 2007

2006

Sequential Equivalence Checking.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Rapid Resource-Constrained Hardware Performance Estimation.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

New approach to architectural synthesis: incorporating QoS constraint.

[BibT_eX]

[DOI]

Harsh Dhand

Basant Kumar Dwivedi

Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006

2005

Integrated On-Chip Storage Evaluation in ASIP Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

ADOPT: An Approach to Activity Based Delay Optimization.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Specialized Graduate Program in VLSI Design Tools and Technology.

[BibT_eX]

[DOI]

B. S. Panwar

Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004

An efficient technique for exploring register file size in ASIP design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Synthesis of Application Specific Multiprocessor Architectures for Process Networks.

[BibT_eX]

[DOI]

Basant Kumar Dwivedi

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Automatic synthesis of system on chip multiprocessor architectures for process networks.

[BibT_eX]

[DOI]

Basant Kumar Dwivedi

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

SoC Synthesis with Automatic Hardware Software Interface Generation.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Exploring Storage Organization in ASIP Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002

A New Divide and Conquer Method for Achieving High Speed Division in Hardware.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Exploring the Number of Register Windows in ASIP Synthesis.

[BibT_eX]

[DOI]

Vishal P. Bhatt

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

A New Performance Evaluation Approach for System Level Design Space Exploration.

[BibT_eX]

[DOI]

C. P. Joshi

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Scratchpad memory: design alternative for cache on-chip memory in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

An efficient technique for exploring register file size in ASIP synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2002

2001

Analysis of the influence of register file size on energyconsumption, code size, and execution time.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study.

[BibT_eX]

[DOI]

Anupam Rastogi

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

ASIP Design Methodologies : Survey and Issues.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

A Specialized Graduate Program in VLSI Design: A Success Story.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

Evaluating register file size in ASIP design.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Exploring design space of parallel realizations: MPEG-2 decoder case study.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000

Allocation of FIFO structures in RTL data paths.

[BibT_eX]

[DOI]

Heman Khanna

ACM Trans. Design Autom. Electr. Syst., 2000

Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

nterface Synthesis: Issues and Approaches.

[BibT_eX]

[DOI]

Arvind Rajawat

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Processor Evaluation in an Embedded Systems Design Environment.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Speeding up power estimation of embedded software.

[BibT_eX]

[DOI]

Akshaye Sama

J. F. M. Theeuwen

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1999

Simulation and Modeling of a Multicast ATM Switch.

[BibT_eX]

[DOI]

Ajoy C. Siddabathuni

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign.

[BibT_eX]

[DOI]

Rashmi Goswami

V. Srinivasan

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Hardware/Software Partitioning Between Microprocessor and Reconfigurable Hardware.

[BibT_eX]

[DOI]

M. Anand

Sanjiv Kapoor

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

1998

Direct mapping of RTL structures onto LUT-based FPGA's.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997

Optimal Clock Period for Synthesized Data Paths.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Novel Reconfigurable Co-Processor Architecture.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1995

Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis.

[BibT_eX]

[DOI]

Alok Kumar

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Buffer constraints in a variable-rate packetized video system.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1995 International Conference on Image Processing, 1995

Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

1994

FAST: FPGA Targeted RTL Structure Synthesis Technique.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

Concurrent Search and Insertion in K-Dimensional Height Balanced Trees.

[BibT_eX]

[DOI]

Atul Varshneya

B. B. Madan

Proceedings of the 8th International Symposium on Parallel Processing, 1994

An Efficient Technique for Mapping RTL Structures onto FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic, 1994

1993

DESSERT: Design Space Exploration of RT Level Components.

[BibT_eX]

[DOI]

M. V. Rao

Proceedings of the Sixth International Conference on VLSI Design, 1993

High Level Design Experiences with IDEAS.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on VLSI Design, 1993

1992

Data Path Synthesis With Global Time Constraint.

[BibT_eX]

[DOI]

Prashant P. Nedungadi

Proceedings of the Fifth International Conference on VLSI Design, 1992

1989

Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration.

[BibT_eX]

[DOI]

Peter Marwedel

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Allocation of multiport memories in data path synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Synthesis of decentralised controllers from high level description.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1988

A Semantic Approach for Modular Synthesis of VLSI Systems.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1988

1986

An efficient retargetable microcode generator.

[BibT_eX]

[DOI]

P. C. P. Bhatt

B. B. Madan

Proceedings of the 19th annual workshop on Microprogramming, 1986

1982

A multi-channel microprogrammed FFT processor.

[BibT_eX]

[DOI]