M. B. Srinivas

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

A smart phone/tablet based mobile health care system for developing countries.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

Uniform approximation of Gaussian wavelet for biomedical signal processing in analog domain.

[BibT_eX]

[DOI]

Goutham Makkena

Prabhakara Rao

Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2012

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.

[BibT_eX]

[DOI]

Goutham Makkena

M. Venkata Swamy Nayudu

Proceedings of the 25th International Conference on VLSI Design, 2012

Design of Prefix-Based Optimal Reversible Comparator.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A Modified Twin Precision Multiplier with 2D Bypassing Technique.

[BibT_eX]

[DOI]

Sibi Abraham

Proceedings of the International Symposium on Electronic System Design, 2012

CNFET based ternary magnitude comparator.

[BibT_eX]

[DOI]

Phaneendra P. Sai

Proceedings of the International Symposium on Communications and Information Technologies, 2012

On the Suitability of Multi-Core Processing for Embedded Automotive Systems.

[BibT_eX]

[DOI]

Santosh Kumar Jena

Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012

2011

A Prefix Based Reconfigurable Adder.

[BibT_eX]

[DOI]

Chetan Kumar V.

Sai Phaneendra P.

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.

[BibT_eX]

[DOI]

Chetan Kumar V.

Proceedings of the International Symposium on Electronic System Design, 2011

A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter.

[BibT_eX]

[DOI]

Krishna Kumar Movva

Proceedings of the International Symposium on Electronic System Design, 2011

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011

A Unified Architecture for BCD and Binary Adder/Subtractor.

[BibT_eX]

[DOI]

Chetan Kumar V.

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.

[BibT_eX]

[DOI]

Sandeep Saini

A. Mahesh Kumar

J. Low Power Electron., 2010

An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.

[BibT_eX]

[DOI]

Sandeep Saini

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A Novel, Variable Resolution Flash ADC with Sub Flash Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Effects of channel SNR in mobile cognitive radios and coexisting deployment of cognitive wireless sensor networks.

[BibT_eX]

[DOI]

Vasanth Iyer

S. Sitharama Iyengar

Garimella Rama Murthy

Nandan Parameswaran

Dhananjay Singh

Proceedings of the 29th International Performance Computing and Communications Conference, 2010

A new approach to minimize leakage power in nano-scale VLSI adder.

[BibT_eX]

[DOI]

Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26, 2010

A low power, variable resolution two-step flash ADC.

[BibT_eX]

[DOI]

Krishna Kumar Movva

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Implementation of low power FFT structure using a method based on conditionally coded blocks.

[BibT_eX]

[DOI]

Sandeep Saini

Anurag Mahajan

Srinivas B. Mandalika

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

An efficient ODT calibration scheme for improved signal integrity in memory interface.

[BibT_eX]

[DOI]

Gudipati Kalyan

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Low power, variable resolution pipelined analog to Digital converter with sub flash architecture.

[BibT_eX]

[DOI]

Krishna Kumar Movva

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Efficient Reversible Logic Design of BCD Subtractors.

[BibT_eX]

[DOI]

Trans. Comput. Sci., 2009

A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter.

[BibT_eX]

[DOI]

J. Low Power Electron., 2009

Design of a Low Power, Variable-Resolution Flash ADC.

[BibT_eX]

[DOI]

Venkat Tummala

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A novel low power, variable resolution pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Multi-hop scheduling and local data link aggregation dependant Qos in modeling and simulation of power-aware wireless sensor networks.

[BibT_eX]

[DOI]

Vasanth Iyer

S. Sitharama Iyengar

Garimella Rama Murthy

Bertrand Hochet

Vir V. Phoha

Proceedings of the International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly, 2009

A High Performance Unified BCD and Binary Adder/Subtractor.

[BibT_eX]

[DOI]

Anshul Singh

Aman Gupta

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex.

[BibT_eX]

[DOI]

Swathi Ramasahayam

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication.

[BibT_eX]

[DOI]

Abinesh Ramachandran

Bharghava Rajaram

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2008

A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks.

[BibT_eX]

[DOI]

Vasanth Iyer

Rammurthy Garimella

Proceedings of the IEEE International Conference on Sensor Networks, 2008

A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection.

[BibT_eX]

[DOI]

Kirthi Krishna Muntimadugu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

New and Improved Architectures for Montgomery Modular Multiplication.

[BibT_eX]

[DOI]

Mob. Networks Appl., 2007

Delay and Energy Efficient Coding Techniques for Capacitive Interconnects.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2007

Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.

[BibT_eX]

[DOI]

Reddy Puppala Sreekanth

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n).

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2007, 2007

Bus encoding schemes for minimizing delay in VLSI interconnects.

[BibT_eX]

[DOI]

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA.

[BibT_eX]

[DOI]

Sudhakar Maddi

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach.

[BibT_eX]

[DOI]

Srinivas Bala Mandalika

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A Comparative Study of Different FFT Architectures for Software Defined Radio.

[BibT_eX]

[DOI]

Shashank Mittal

Md. Zafar Ali Khan

Proceedings of the Embedded Computer Systems: Architectures, 2007

Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs.

[BibT_eX]

[DOI]

Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.

[BibT_eX]

[DOI]

Reddy Puppala Sreekanth

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Novel High-Speed Redundant Binary to Binary converter using Prefix Networks.

[BibT_eX]

[DOI]

Reddy Puppala Sreekanth

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN).

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Novel architectures for efficient (m, n) parallel counters.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Area Efficient High Speed Architecture of Bruun's FFT for Software Defined Radio.

[BibT_eX]

[DOI]

Shashank Mittal

Md. Zafar Ali Khan

Proceedings of the Global Communications Conference, 2007

Rule Selection in Fuzzy Systems using Heuristics and Branch Prediction.

[BibT_eX]

[DOI]

Keerthi Laal Kala

Proceedings of the IEEE Symposium on Foundations of Computational Intelligence, 2007

A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format

[BibT_eX]

[DOI]

CoRR, 2006

VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics

[BibT_eX]

[DOI]

CoRR, 2006

Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU

[BibT_eX]

[DOI]

CoRR, 2006

An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates

[BibT_eX]

[DOI]

CoRR, 2006

A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits

[BibT_eX]

[DOI]

CoRR, 2006

Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.

[BibT_eX]

[DOI]

Saurabh Kotiyal

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

High-Throughput Montgomery Modular Multiplication.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n).

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations.

[BibT_eX]

Pallavi Devi Gopineedi

Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

A Generic Architecture for Intelligent System Hardware.

[BibT_eX]

[DOI]

Keerthi Laal Kala

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Novel Reversible Multiplier Architecture Using Reversible TSG Gate.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

The New BCD Subtractor and Its Reversible Logic Implementation.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005

Local Language Support for Handheld Devices.

[BibT_eX]

[DOI]

Yaswanth Narvaneni

Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

A 32-Bit Binary Floating Point Neuro-Chip.

[BibT_eX]

[DOI]

Keerthi Laal Kala

Proceedings of the Advances in Natural Computation, First International Conference, 2005

A novel deep submicron low power bus coding technique.

[BibT_eX]

Proceedings of the Third IASTED International Conference on Circuits, 2005

Implementation of A Fast Square In RSA Encryption/Decryption Architecture.

[BibT_eX]

Proceedings of The 2005 International Conference on Security and Management, 2005

Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier.

[BibT_eX]

Proceedings of The 2005 International Conference on Security and Management, 2005

Reversible Logic Synthesis of Half, Full and Parallel Subtractors.

[BibT_eX]

Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs.

[BibT_eX]

Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor.

[BibT_eX]

Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison.

[BibT_eX]

Proceedings of The 2005 International Conference on Scientific Computing, 2005

Verilog Coding Style for Efficient Synthesis In FPGA.

[BibT_eX]

Proceedings of the 2005 International Conference on Computer Design, 2005

Design for A Fast And Low Power 2's Complement Multiplier.

[BibT_eX]

Proceedings of the 2005 International Conference on Computer Design, 2005

Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture.

[BibT_eX]

Proceedings of the 2005 International Conference on Algorithmic Mathematics and Computer Science, 2005

A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2003

Design of a digital CDMA receiver.

[BibT_eX]

[DOI]

I. Vijay Kumar

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Speech encoding and encryption in VLSI.

[BibT_eX]

[DOI]

K. Kalyan Chakravarthy