M. B. Ghaznavi-Ghoushchi
Orcid: 0000-0001-7026-9476
According to our database1,
M. B. Ghaznavi-Ghoushchi
authored at least 62 papers
between 2008 and 2024.
Collaborative distances:
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Bibliography
2024
Design and Analysis of a New Three-Stage Feedback Amplifier Utilizing Signal Flow Graph Domain Inspection Approach.
IEEE Trans. Very Large Scale Integr. Syst., October, 2024
An Unconditional Evenly Spaced STRO With a New Mitigated Drafting Effect Muller C-Element.
IEEE Trans. Very Large Scale Integr. Syst., August, 2024
QD-PFD: Quasi Dynamic Dead-Zone/Blind-Zone Free PFD With 23 nW-38 μW for 2 MHz-5 GHz Range and 150-ns Settling Time PLL Applications.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
2023
Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023
Analysis and Extraction of Tempo-Spatial Events in an Efficient Archival CDN with Emphasis on Telegram.
CoRR, 2023
2022
AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
ML-Based Aging Monitoring and Lifetime Prediction of IoT Devices With Cost-Effective Embedded Tags for Edge and Cloud Operability.
IEEE Internet Things J., 2022
A novel generic modulo-2 graph with full set taxonomical conversion to parallel prefix adders.
Int. J. Circuit Theory Appl., 2022
A power-performance partitioning approach for low-power DA-based FIR filter design with emphasis on datapath and controller.
Int. J. Circuit Theory Appl., 2022
AI Annotated Recommendations in an Efficient Visual Learning Environment with Emphasis on YouTube (AI-EVL).
CoRR, 2022
2021
A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency.
Microelectron. J., 2021
J. Circuits Syst. Comput., 2021
Low-voltage and high-speed stand-alone multiple-input complex gates for error correction coding applications.
Int. J. Circuit Theory Appl., 2021
A New Low Power Schema for Stream Processors Front-End with Power-Aware DA-Based FIR Filters by Investigation of Image Transitions Sparsity.
Circuits Syst. Signal Process., 2021
2020
An Ultra-Low Power Programmable Current Gain Amplifier with a Novel Current Gain Controller Structure for IoT Applications.
Wirel. Pers. Commun., 2020
PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020
An energy-efficient threshold voltage extractor with the burst-mode operation and extended long-term variations using FVF.
Microelectron. J., 2020
2019
Wirel. Pers. Commun., 2019
Optimistic Modeling and Simulation of Complex Hardware Platforms and Embedded Systems on Many-Core HPC Clusters.
IEEE Trans. Parallel Distributed Syst., 2019
J. Supercomput., 2019
A DPA Attack on IOA Data-Dependent Delay Countermeasure Based on an Inherent Tempo-Spatial Data Dependency.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A low-power and high-speed parallel binary comparator based on inter-stage modified binary tree structure and power-delay improved cell elements.
Microelectron. J., 2019
Design of low-voltage shallow-depth differential source coupled logic using feedback and feedforward techniques.
Microelectron. J., 2019
A fully pipelined and parallel hardware architecture for real-time BRISK salient point extraction.
J. Real Time Image Process., 2019
2018
An output node split CMOS logic for high-performance and large capacitive-load driving scenarios.
Microelectron. J., 2018
NEMR: A Nonequidistant DPA Attack-Proof of Modular Reduction in a CRT Implementation of RSA.
J. Circuits Syst. Comput., 2018
A low-area, 43.5% PAE, 0.9 W, Class-E differential power amplifier in 2.4 GHz for IoT applications.
Integr., 2018
An ultra low-power current-mode clock and data recovery design with input bit-rate adaptability for biomedical applications in CMOS 90 nm.
Integr., 2018
A power-performance tunable logic with adjustable threshold pseudo-dynamic building blocks and CMOS compatibility.
Int. J. Circuit Theory Appl., 2018
Low-complexity and differential power analysis (DPA)-resistant two-folded power-aware Rivest-Shamir-Adleman (RSA) security schema implementation for IoT-connected devices.
IET Comput. Digit. Tech., 2018
2017
A Novel Fully Differential CMOS Class-E Power Amplifier with Higher Output Power and Efficiency for IoT Application.
Wirel. Pers. Commun., 2017
A Process-Independent and Highly Linear DCO for Crowded Heterogeneous IoT Devices in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2017
MTCML: Analysis, design and optimization of an alternative shallow-depth multiple-tail current mode logic.
Microelectron. J., 2017
The Parvicursor infrastructure to facilitate the design of Grid and Cloud computing systems.
Computing, 2017
A novel transceiver structure including power and audio amplifiers for Internet of Things applications.
Comput. Electr. Eng., 2017
2016
Microelectron. J., 2016
Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm.
J. Electronic Imaging, 2016
Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm.
Circuits Syst. Signal Process., 2016
2015
A new secure Internet voting protocol using Java Card 3 technology and Java information flow concept.
Secur. Commun. Networks, 2015
Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits.
Microelectron. Reliab., 2015
2014
VLSI implementation of star detection and centroid calculation algorithms for star tracking applications.
J. Real Time Image Process., 2014
Design and implementation of a novel secure internet voting protocol using Java Card 3 technology.
Int. J. Bus. Inf. Syst., 2014
Personalized recommendation of learning material using sequential pattern mining and attribute based collaborative filtering.
Educ. Inf. Technol., 2014
A New Low-Power Architecture Design for Distributed Arithmetic Unit in FIR Filter Implementation.
Circuits Syst. Signal Process., 2014
2013
An Effective Recommendation Framework for Personal Learning Environments Using a Learner Preference Tree and a GA.
IEEE Trans. Learn. Technol., 2013
Attribute-based collaborative filtering using genetic algorithm and weighted C-means algorithm.
Int. J. Bus. Inf. Syst., 2013
Self-impact of NBTI effect on the degradation rate of threshold voltage in PMOS transistors.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
2012
An Improved Watchdog Technique Based On Power-Aware Hierarchical Design For Ids In Wireless Sensor Networks
CoRR, 2012
Comput. Electr. Eng., 2012
Proceedings of the 6th International Symposium on Telecommunications, 2012
2011
An ultra low-power digitally controlled oscillator using novel Schmitt-trigger based hysteresis delay cells.
IEICE Electron. Express, 2011
An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator.
IEICE Electron. Express, 2011
A new low-power, low-area, parallel prefix Sklansky adder with reduced inter-stage connections complexity.
Proceedings of EUROCON 2011, 2011
Proceedings of EUROCON 2011, 2011
2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2008
Proceedings of the Advances in Computer Science and Engineering, 2008