M. Aline

According to our database, M. Aline authored at least 4 papers between 1999 and 2003.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2003

MVL circuit design and characterization at the transistor level using SUS-LOC.

E. Kinvi-Boh, M. Aline, Olivier Sentieys, Edgar "Dan" Olson

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

2001

Delay bound determination for timing closure satisfaction.

Nadine Azémard, M. Aline, Daniel Auvergne

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Feasible Delay Bound Definition.

Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne

Proceedings of the SOC Design Methodologies, 2001

1999

Delay-power performance analysis.

S. Cremoux, M. Aline, Nadine Azémard, Daniel Auvergne

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999