Luz Balado

According to our database1, Luz Balado authored at least 18 papers between 2002 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Indirect and adaptive test of analogue circuits based on preselected steady-state response measures.
IET Circuits Devices Syst., 2020

2017
Multi-Directional Space Tessellation to Improve the Decision Boundary in Indirect Mixed-Signal Testing.
J. Electron. Test., 2017

2016
Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Indirect test of M-S circuits using multiple specification band guarding.
Integr., 2016

2015
Analog circuits testing using digitally coded indirect measurements.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014
M-S specification binning based on digitally coded indirect measurements.
Proceedings of the 19th IEEE European Test Symposium, 2014

2013
M-S test based on specification validation using octrees in the measure space.
Proceedings of the 18th IEEE European Test Symposium, 2013

2010
Analog circuit test based on a digital signature.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2006
Lissajous Based Mixed-Signal Testing for N-Observable Signals.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
Testing Biquad Filters under Parametric Shifts Using X-Y Zoning.
J. Electron. Test., 2005

2004
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.
J. Electron. Test., 2004

Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.
J. Electron. Test., 2004

BIST Technique by Equally Spaced Test Vector Sequences.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003
Test Engineering Education in Europe: the EuNICE-Test Project.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

On the selection of efficient arithmetic additive test pattern generators [logic test].
Proceedings of the 8th European Test Workshop, 2003

2002
On High-Quality, Low Energy BIST Preparation at RT-Level.
Proceedings of the 3rd Latin American Test Workshop, 2002


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