Lutong Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

TritonRoute: The Open-Source Detailed Router.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

WSHE: User feedback-based weighted signed heterogeneous information network embedding.

[BibT_eX]

[DOI]

Baofang Hu

Hong Wang

Inf. Sci., 2021

2020

Improved Physical Design for Manufacturing Awareness and Advanced VLSI

[BibT_eX]

[DOI]

PhD thesis, 2020

Feature-maximum-dependency-based fusion diagnosis method for COPD.

[BibT_eX]

[DOI]

Multim. Tools Appl., 2020

Memory model for web ad effect based on multimodal features.

[BibT_eX]

[DOI]

J. Assoc. Inf. Sci. Technol., 2020

On the superiority of modularity-based clustering for determining placement-relevant clusters.

[BibT_eX]

[DOI]

Integr., 2020

Impression space model for the evaluation of Internet advertising effectiveness.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2020

Diagnosis of Chronic Obstructive Pulmonary Disease Based on Transfer Learning.

[BibT_eX]

[DOI]

IEEE Access, 2020

The Tao of PAO: Anatomy of a Pin Access Oracle for Detailed Routing.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10 nm VLSI.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

RePlAce: Advancing Solution Quality and Routability Validation in Global Placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

MCPL-Based FT-LSTM: Medical Representation Learning-Based Clinical Prediction Model for Time Series Events.

[BibT_eX]

[DOI]

IEEE Access, 2019

Diagnosis of COPD Based on a Knowledge Graph and Integrated Model.

[BibT_eX]

[DOI]

IEEE Access, 2019

2019 CAD Contest: LEF/DEF Based Global Routing.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Diffusion break-aware leakage power optimization and detailed placement in sub-10nm VLSI.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Finding placement-relevant clusters with fast modularity-based clustering.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Wide and Deep Model of Multi-Source Information-Aware Recommender System.

[BibT_eX]

[DOI]

IEEE Access, 2018

Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

Predictor-based feedback for discrete-time linear system with sawtooth-like input delay.

[BibT_eX]

[DOI]

Jian Sun

Jie Chen

Proceedings of the IEEE International Conference on Information and Automation, 2018

TritonRoute: an initial detailed router for advanced VLSI technologies.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Integrated Prediction Method for Mental Illness with Multimodal Sleep Function Indicators.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2018

Detecting Fake Reviews Based on Review-Rating Consistency and Multi-dimensional Time Series.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2018

2017

MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Improved flop tray-based design implementation for power reduction.

[BibT_eX]

[DOI]

Jiajia Li