Lun-Yao Wang

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2024
Semi-Tensor Product-Based Exact Synthesis for Logic Rewriting.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

A Semi-Tensor Product based Circuit Simulation for SAT-sweeping.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2022
2022 roadmap on neuromorphic devices and applications research in China.
Neuromorph. Comput. Eng., December, 2022

Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2022

2021
BCD Adder Designs Based on Three-Input XOR and Majority Gates.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
Advanced Functional Decomposition Using Majority and Its Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A High-Performance Design of Generalized Pipeline Cellular Array.
IEEE Comput. Archit. Lett., 2020

2019
Multi-objective algebraic rewriting in XOR-majority graphs.
Integr., 2019

Exact Synthesis of Boolean Functions in Majority-of-Five Forms.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Structural rewriting in XOR-majority graphs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Area Optimization of MPRM Circuits Using Approximate Computing.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Power optimization for FPRM logic using approximate computing technique.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2016
Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence.
Integr., 2016

Efficient power pad assignment for multi-voltage SoC and its application in floorplanning.
Int. J. Circuit Theory Appl., 2016

2014
Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine.
Microelectron. J., 2014

Level shifter planning for timing constrained multi-voltage SoC floorplanning.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013
Low Power State Assignment Algorithm for FSMs Considering Peak Current Optimization.
J. Comput. Sci. Technol., 2013

Logic Minimization Based on Dual Logic.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

2012
Cell Mapping for Nanohybrid Circuit Architecture Using Genetic Algorithm.
J. Comput. Sci. Technol., 2012

2011
Reed-Muller function optimization techniques with onset table.
J. Zhejiang Univ. Sci. C, 2011

2010
A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2005
Novel Synthesis and Optimization of Multi-Level Mixed Polarity Reed-Muller Functions.
J. Comput. Sci. Technol., 2005

A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock.
J. Comput. Sci. Technol., 2005

Novel synthesis method of mixed polarity Reed-Muller functions.
Proceedings of the Third IASTED International Conference on Circuits, 2005


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