Lukasz G. Szafaryn
According to our database1,
Lukasz G. Szafaryn
authored at least 8 papers
between 2010 and 2019.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
2018
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2016
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
2013
IEEE Micro, 2013
J. Parallel Distributed Comput., 2013
2010
A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010