Lukás Nagy

Orcid: 0000-0002-9440-7025

According to our database1, Lukás Nagy authored at least 39 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
Design of Ultra-Low Power Comparator in 65 NM CMOS Technology with Rail-to-Rail Input Range.
Proceedings of the IEEE AFRICON 2023, Nairobi, Kenya, September 20-22, 2023, 2023

2022
Low-Power Rail-to-Rail Comparator in 130 nm CMOS Technology.
Proceedings of the 32nd International Conference Radioelektronika, 2022

High Power Supply Rejection LDO Regulator for Switching Applications.
Proceedings of the 45th Jubilee International Convention on Information, 2022

2021
Low-Voltage DC-DC Converter for IoT and On-Chip Energy Harvester Applications.
Sensors, 2021

Maximum Power Point Tracking Circuit for an Energy Harvester in 130 nm CMOS Technology.
CoRR, 2021

Fully On-Chip Low-Drop Regulator for Low-Power Applications.
Proceedings of the 44th International Convention on Information, 2021

EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven IC Design.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

EKV Model for Bulk-Driven Circuit Design Using gmb/ID Method.
Proceedings of the 2021 IEEE AFRICON, 2021

2020
Low-Leakage ESD Structures in 130nm CMOS Technology.
Proceedings of the 30th International Conference Radioelektronika, 2020

Multi-Topology DC-DC Converter for Low-Voltage Energy Harvesting Systems.
Proceedings of the 43rd International Convention on Information, 2020

RED-based Scheduler on Chip for Mixed-Criticality Real-Time Systems.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

Dynamic Properties Of Ultra Low-Voltage Rail-to-Rail Comparator Designed In 130 nm CMOS Technology.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019
A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems.
J. Circuits Syst. Comput., 2019

Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells Comprising D- and E-Mode HEMTs.
J. Circuits Syst. Comput., 2019

Towards Energy-autonomous Integrated Systems Through Ultra-low Voltage Analog IC Design.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Neural Network for Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Gates.
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Performance Analysis Of Ultra Low-Voltage Rail-to-Rail Comparator In 130 nm CMOS Technology.
Proceedings of the 2019 IEEE AFRICON, Accra, Ghana, September 25-27, 2019, 2019

2018
Device and circuit models of InAlN/GaN D- and dual-gate E-mode HEMTs for design and characterisation of monolithic NAND logic cell.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

A Novel Hardware-Accelerated Priority Queue for Real-Time Systems.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Two-Stage Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017
A Novel Method Towards Time-Efficient Fault Analysis of Analog and Mixed-Signal Circuits.
J. Circuits Syst. Comput., 2017

130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications.
J. Circuits Syst. Comput., 2017

Low-power bulk-driven rail-to-rail comparator in 130 nm CMOS technology.
Proceedings of the IEEE AFRICON 2017, Cape Town, South Africa, September 18-20, 2017, 2017

2016
Variable-gain amplifier for ultra-low voltage applications in 130nm CMOS technology.
Proceedings of the 39th International Convention on Information and Communication Technology, 2016

Impedance calculation based method for AC fault analysis of mixed-signal circuits.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Readout interface for capacitive MEMS microphone in CMOS technology.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Design of In AlN/GaN Heterostructure-Based Logic Cells.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
Current Sensing Completion Detection in Single-Rail Asynchronous Systems.
Comput. Informatics, 2014

3-D electrothermal device/circuit simulation of DC-DC converter module in multi-die IC.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Novel architecture of a digital neuron for FFNN employing special multiplication.
Proceedings of the ECAI 2014 - 21st European Conference on Artificial Intelligence, 18-22 August 2014, Prague, Czech Republic, 2014

2013
Completion detection in dual-rail asynchronous systems by current-sensing.
Microelectron. J., 2013

2012
Current sensing completion detection in dual-rail asynchronous systems.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Current sensing methodology for completion detection in self-timed systems.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Current Sensing Completion Detection in deep sub-micron technologies.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010


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