Lukás Kohútka

Orcid: 0000-0002-5679-6250

Affiliations:
  • Slovak University of Technology in Bratislava, Slovakia


According to our database1, Lukás Kohútka authored at least 23 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Lockstep Vs Microarchitecture: A Comparison.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Influence of Structural Units on Vulnerability of Systems with Distinct Protection Approaches.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

Interface Protection Against Transient Faults.
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

2023
Scheduling Tool for Deterministic Communication in Distributed Real-Time Systems.
Proceedings of the Tenth Workshop on Software Quality Analysis, 2023

Hardened Processor Architecture.
Proceedings of the 30th International Conference on Mixed Design of Integrated Circuits and System, 2023

A New RISC-V CPU for Safety-Critical Systems.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

2022
A New FPGA - based Architecture of Task Scheduler with Support of Periodic Real-Time Tasks.
Proceedings of the 29th International Conference on Mixed Design of Integrated Circuits and System, 2022

Scheduling Periodic Real-Time Tasks with Inter-Task Synchronisation.
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022

2020
Novel efficient on-chip task scheduler for multi-core hard real-time systems.
Microprocess. Microsystems, 2020

ASIC Architecture and Implementation of RED Scheduler for Mixed-Criticality Real-Time Systems.
Proceedings of the 27th International Conference on Mixed Design of Integrated Circuits and System, 2020

RED-based Scheduler on Chip for Mixed-Criticality Real-Time Systems.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

2019
A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems.
J. Circuits Syst. Comput., 2019

A New Hardware-Accelerated Scheduler for Soft Real-Time Tasks.
Proceedings of the 8th Mediterranean Conference on Embedded Computing, 2019

Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018
Reliable real-time task scheduler based on Rocket Queue architecture.
Microelectron. Reliab., 2018

A novel hardware-accelerated real-time task scheduler based on robust earliest deadline algorithm.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

A Novel Hardware-Accelerated Priority Queue for Real-Time Systems.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Heap Queue: A Novel Efficient Hardware Architecture of MIN/MAX Queues for Real-Time Systems.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017
A new efficient sorting architecture for real-time systems.
Proceedings of the 6th Mediterranean Conference on Embedded Computing, 2017

Rocket Queue: New data sorting architecture for real-time systems.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
Task scheduler for dual-core real-time systems.
Proceedings of the 2016 MIXDES, 2016

Improved Task Scheduler for Dual-Core Real-Time Systems.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
Hardware Accelerated Scheduling in Real-Time Systems.
Proceedings of the 2015 4th Eastern European Regional Conference on the Engineering of Computer Based Systems, 2015


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