Lukas Kekely

According to our database, Lukas Kekely authored at least 20 papers between 2012 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks.

Tomás Fukac, Jirí Matousek, Jan Korenek, Lukás Kekely

Proceedings of the International Conference on Field-Programmable Technology, 2021

2020

General memory efficient packet matching FPGA architecture for future high-speed networks.

Michal Kekely, Lukás Kekely, Jan Korenek

Microprocess. Microsystems, 2020

Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs.

Lukás Kekely, Jakub Cabal, Viktor Pus, Jan Korenek

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019

Effective FPGA Architecture for General CRC.

Lukás Kekely, Jakub Cabal, Jan Korenek

Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

2018

Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers.

Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek

Proceedings of the 2018 IEEE/IFIP Network Operations and Management Symposium, 2018

General IDS Acceleration for High-Speed Networks.

Jan Kucera, Lukas Kekely, Adam Piecek, Jan Korenek

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput.

Lukás Kekely, Martin Spinler, Stepán Friedl, Jiri Sikora, Jan Korenek, Viktor Pus

Proceedings of the International Conference on Field-Programmable Technology, 2018

High-Speed Computation of CRC Codes for FPGAs.

Jakub Cabal, Lukás Kekely, Jan Korenek

Proceedings of the International Conference on Field-Programmable Technology, 2018

Accelerated Wire-Speed Packet Capture at 200 Gbps.

Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.

Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Memory Aware Packet Matching Architecture for High-Speed Networks.

Michal Kekely, Lukas Kekely, Jan Korenek

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2016

Software Defined Monitoring of Application Protocols.

Lukas Kekely, Jan Kucera, Viktor Pus, Jan Korenek, Athanasios V. Vasilakos

IEEE Trans. Computers, 2016

2015

Hardware accelerated flow measurement of 100 Gb ethernet.

Viktor Pus, Petr Velan, Lukas Kekely, Jan Korenek, Pavel Minarík

Proceedings of the IFIP/IEEE International Symposium on Integrated Network Management, 2015

2014

Software Defined Monitoring of application protocols.

Lukas Kekely, Viktor Pus, Jan Korenek

Proceedings of the 2014 IEEE Conference on Computer Communications, 2014

Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring.

Lukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Using DSP blocks to compute CRC hash in FPGA (abstract only).

Viktor Pus, Lukas Kekely, Tomás Závodník

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

CRC based hashing in FPGA using DSP blocks.

Tomás Závodník, Lukas Kekely, Viktor Pus

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Design methodology of configurable high performance packet parser for FPGA.

Viktor Pus, Lukas Kekely, Jan Korenek

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Fast lookup for dynamic packet filtering in FPGA.

Lukas Kekely, Martin Zádník, Jirí Matousek, Jan Korenek

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2012

Low-latency modular packet header parser for FPGA.

Viktor Pus, Lukas Kekely, Jan Korenek

Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012