Lukas Jünger
Orcid: 0000-0001-9149-1690Affiliations:
- RWTH Aachen University, Institute for Communication Technologies and Embedded Systems, Germany
According to our database1,
Lukas Jünger
authored at least 16 papers
between 2019 and 2024.
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Bibliography
2024
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024
Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023
Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TlM-2.0-Based Virtual Platforms.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023
2022
Int. J. Parallel Program., 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
2021
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, 2019