Luis Quintanilla

According to our database, Luis Quintanilla authored at least 14 papers between 2001 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Automated Machine Learning & Tuning with FLAML.

Chi Wang, Qingyun Wu, Xueqing Liu, Luis Quintanilla

Proceedings of the KDD '22: The 28th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, Washington, DC, USA, August 14, 2022

2013

Effect of Finite amplifier Bandwidth and excess Loop Delay in a Parallel CT δς ADC for OFDM UWB receivers.

Luis Quintanilla, Jesús Arias Álvarez, Jokin Segundo, Lourdes Enríquez, Jesús Manuel Hernández-Mangas, José Vicente

J. Circuits Syst. Comput., 2013

2012

A 1.2 V, 130 nm CMOS parallel continuous-time ΣΔ ADC for OFDM UWB receivers.

Jokin Segundo, Jesús Arias Álvarez, Luis Quintanilla, Lourdes Enríquez, Jesús Manuel Hernández-Mangas, José Vicente

Microelectron. J., 2012

2011

Detailed analysis of the effect of a hysteretic quantizer in a multibit, Sigma-Delta modulator.

Luis Quintanilla, Jesús Arias Álvarez, Jokin Segundo, Lourdes Enríquez, Jesús Manuel Hernández-Mangas, José Vicente

Microelectron. J., 2011

A parallel, CT-ΔΣ based ADC for OFDM UWB receivers in 130 nm CMOS.

Jokin Segundo, Jesús Arias Álvarez, Luis Quintanilla, Lourdes Enríquez, Jesús Manuel Hernández-Mangas, José Vicente

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2009

Parallel Continuous-Time DeltaSigma ADC for OFDM UWB Receivers.

Jesús Arias Álvarez, Luis Quintanilla, Jokin Segundo, Lourdes Enríquez, José Vicente, Jesús Manuel Hernández-Mangas

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A comprehensive analysis of the effect of finite amplifier bandwidth and excess loop delay in continuous-time sigma-delta modulators.

Luis Quintanilla, Jesús Arias Álvarez, Jokin Segundo, Lourdes Enríquez, Jesús Manuel Hernández-Mangas, José Vicente

Microelectron. J., 2009

A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.

Jokin Segundo, Luis Quintanilla, Jesús Arias Álvarez, Lourdes Enríquez, Jesús Manuel Hernández-Mangas, José Vicente

Integr., 2009

2008

A 1-GHz, multibit, continuous-time, delta-sigma ADC for Gigabit Ethernet.

Jesús Arias Álvarez, Luis Quintanilla, Lourdes Enríquez, Jesús Manuel Hernández-Mangas, José Vicente, Jokin Segundo

Microelectron. J., 2008

2006

A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers.

Jesús Arias Álvarez, Peter Kiss, Vladimir I. Prodanov, Vito Boccuzzi, Mihai Banu, David Bisbal, Jacinto San Pablo, Luis Quintanilla, Juan Barbolla

IEEE J. Solid State Circuits, 2006

2005

Nonlinearity correction for multibit ΔΣ DACs.

Jesús Arias Álvarez, Peter Kiss, Vito Boccuzzi, Luis Quintanilla, Lourdes Enríquez, José Vicente, David Bisbal, Jacinto San Pablo, Juan Barbolla

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2004

Low-power pipeline ADC for wireless LANs.

Jesús Arias Álvarez, Vito Boccuzzi, Luis Quintanilla, Lourdes Enríquez, David Bisbal, Mihai Banu, Juan Barbolla

IEEE J. Solid State Circuits, 2004

2002

Design of a switched opamp-based bandpass filter in a 0.35 μm CMOS technology.

Luis Quintanilla, Jesús Arias Álvarez, Lourdes Enríquez, José Vicente, Juan Barbolla, Diego Vázquez, Adoración Rueda

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

Design of a CMOS fully differential switched-opamp for SC circuits at very low power supply voltages.

Jesús Arias Álvarez, Luis Quintanilla, Lourdes Enríquez, José Vicente, Juan Barbolla, Diego Vázquez, Adoración Rueda

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001