Luigi Dilillo

Carolina Imianosky

Proceedings of the 9th International Workshop on Advances in Sensors and Interfaces, 2023

Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip.

[BibT_eX]

[DOI]

Benjamin W. Mezger

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Implementation and Reliability Evaluation of a RISC-V Vector Extension Unit.

[BibT_eX]

[DOI]

Carolina Imianosky

Felipe Viel

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression.

[BibT_eX]

[DOI]

Wesley Grignani

Felipe Viel

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022

Emulating the Effects of Radiation-Induced Soft-Errors for the Reliability Assessment of Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

A Survey of the RISC-V Architecture Software Support.

[BibT_eX]

[DOI]

Benjamin W. Mezger

Cesar A. Zeferino

IEEE Access, 2022

Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021

Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Characterization of a RISC-V System-on-Chip under Neutron Radiation.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router.

[BibT_eX]

[DOI]

Douglas Rossi Melo

César Albenes Zeferino

Eduardo Augusto Bezerra

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Technology Impact on Neutron-Induced Effects in SDRAMs: A Comparative Study.

[BibT_eX]

[DOI]

Lucas Matana Luza

Daniel Söderström

Douglas Almeida dos Santos

Eduardo Augusto Bezerra

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

A Model-Based Framework to Assess the Reliability of Safety-Critical Applications.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020

A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems.

[BibT_eX]

[DOI]

Lucas Matana Luza

César Albenes Zeferino

Douglas Rossi de Melo

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM.

[BibT_eX]

[DOI]

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems.

[BibT_eX]

[DOI]

Lucas Matana Luza

Daniel Söderström

Elder Dominghini Tramontin

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design.

[BibT_eX]

[DOI]

Sensors, 2019

A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites.

[BibT_eX]

[DOI]

Cezar Antônio Rigo

Lucas M. Luza

Victor M. Goncalves Martins

Sara Vega Martínez

Leonardo Kessler Slongo

Proceedings of the IEEE Latin American Test Symposium, 2019

Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router.

[BibT_eX]

[DOI]

Douglas Rossi de Melo

César Albenes Zeferino

Eduardo Augusto Bezerra

Proceedings of the IEEE Latin American Test Symposium, 2019

Design and Implementation of a Flexible Interface for TID Detector.

[BibT_eX]

[DOI]

Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019

Effects of Heavy Ion and Proton Irradiation on a SLC NAND Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Characterization of a RISC-V Microcontroller Through Fault Injection.

[BibT_eX]

[DOI]

Dario Asciolla

Alessandra Menicucci

Marco Ottavi

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018

Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017

A calculation method to estimate single event upset cross section.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2017

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2017

Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE European Test Symposium, 2017

2016

Design for Test and Diagnosis of Power Switches.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

An effective BIST architecture for power-gating mechanisms in low-power SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

Real-time SRAM based particle detector.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015

An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

An effective hybrid fault-tolerant architecture for pipelined cores.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

Scan-chain intra-cell defects grading.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

An effective ATPG flow for Gate Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Design-for-Diagnosis Architecture for Power Switches.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Exploring the impact of functional test programs re-used for power-aware testing.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Globally Constrained Locally Optimized 3-D Power Delivery Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

On the Test and Mitigation of Malfunctions in Low-Power SRAMs.

[BibT_eX]

[DOI]

J. Electron. Test., 2014

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems.

[BibT_eX]

[DOI]

J. Electron. Test., 2014

Intra-Cell Defects Diagnosis.

[BibT_eX]

[DOI]

Etienne Auvray

J. Electron. Test., 2014

TSV aware timing analysis and diagnosis in paths with multiple TSVs.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A Comprehensive Evaluation of Functional Programs for Power-Aware Test.

[BibT_eX]

[DOI]

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

iBoX - Jitter based Power Supply Noise sensor.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Test and diagnosis of power switches.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Timing-aware ATPG for critical paths with multiple TSVs.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

An intra-cell defect grading tool.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

On the Generation of Diagnostic Test Set for Intra-cell Defects.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

A Study of Tapered 3-D TSVs for Power and Thermal Integrity.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption.

[BibT_eX]

[DOI]

J. Low Power Electron., 2013

A built-in scheme for testing and repairing voltage regulators of low-power srams.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains.

[BibT_eX]

[DOI]

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Characterization of an SRAM based particle detector for mixed-field radiation environments.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

Effect-cause intra-cell diagnosis at transistor level.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

Computing detection probability of delay defects in signal line tsvs.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell.

[BibT_eX]

[DOI]

Elena I. Vatajelu

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Test solution for data retention faults in low-power SRAMs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC<sup>TM</sup> eFlash Memories.

[BibT_eX]

[DOI]

Gilles Festes

Laurent Vachez

J. Electron. Test., 2012

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

A pseudo-dynamic comparator for error detection in fault tolerant architectures.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Advanced test methods for SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low-power SRAMs power mode control logic: Failure analysis and test solutions.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Evaluation of test algorithms stress effect on SRAMs under neutron radiation.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Defect analysis in power mode control logic of low-power SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

Through-Silicon-Via resistive-open defect analysis.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

Coupling-based resistive-open defects in TAS-MRAM architectures.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

Impact of resistive-open defects on the heat current of TAS-MRAM architectures.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Power Supply Noise Sensor Based on Timing Uncertainty Measurements.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Why and How Controlling Power Consumption during Test: A Survey.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Peak Power Estimation: A Case Study on CPU Cores.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Impact of Resistive-Bridge Defects in TAS-MRAM Architectures.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Versatile march test generator for hands-on memory testing laboratory.

[BibT_eX]

[DOI]

Jean-Marc Gallière

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench.

[BibT_eX]

[DOI]

Proceedings of the 12th Latin American Test Workshop, 2011

On using address scrambling to implement defect tolerance in SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

A study of path delay variations in the presence of uncorrelated power and ground supply noise.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

On using a SPICE-like TSTAC™ eFlash model for design and test.

[BibT_eX]

[DOI]

Gilles Festes

Laurent Vachez

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Failure Analysis and Test Solutions for Low-Power SRAMs.

[BibT_eX]

[DOI]

Aida Todri

Proceedings of the 20th IEEE Asian Test Symposium, 2011

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Power-Aware Test Pattern Generation for At-Speed LOS Testing.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.

[BibT_eX]

[DOI]

J. Low Power Electron., 2010

Detecting NBTI induced failures in SRAM core-cells.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Is test power reduction through X-filling good enough?

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Parity prediction synthesis for nano-electronic gate designs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

A roaming memory test bench for detecting particle induced SEUs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts.

[BibT_eX]

[DOI]

Alessandro Paccagnella

Matteo Sonza Reorda

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

A two-layer SPICE model of the ATMEL TSTAC<sup>TM</sup> eFlash memory technology for defect injection and faulty behavior prediction.

[BibT_eX]

[DOI]

Gilles Festes

Laurent Vachez

Proceedings of the 15th European Test Symposium, 2010

Setting test conditions for improving SRAM reliability.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Impact of Resistive-Bridging Defects in SRAM Core-Cell.

[BibT_eX]

[DOI]

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A statistical simulation method for reliability analysis of SRAM core-cells.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

A Memory Fault Simulator for Radiation-Induced Effects in SRAMs.

[BibT_eX]

[DOI]

Paolo Rech

Proceedings of the 19th IEEE Asian Test Symposium, 2010

A Comprehensive System-on-Chip Logic Diagnosis.

[BibT_eX]

[DOI]

Olivia Riewer

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

NAND flash testing: A preliminary study on actual defects.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

Comprehensive bridging fault diagnosis based on the SLAT paradigm.

[BibT_eX]

[DOI]

Laroussi Bouzaida

Isabelle Izaute

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

A new design-for-test technique for SRAM core-cell stability faults.

[BibT_eX]

[DOI]

Alexandre Ney

Vincent Gouin

Proceedings of the Design, Automation and Test in Europe, 2009

Delay Fault Diagnosis in Sequential Circuits.

[BibT_eX]

[DOI]

Olivia Riewer

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

March CRF: an Efficient Test for Complex Read Faults in SRAM Memories.

[BibT_eX]

[DOI]

Bashir M. Al-Hashimi

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Reducing Power Dissipation in SRAM during Test.

[BibT_eX]

[DOI]

J. Low Power Electron., 2006

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.

[BibT_eX]

[DOI]

J. Electron. Test., 2006

March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Minimizing test power in SRAM through reduction of pre-charge activity.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.

[BibT_eX]

[DOI]

Magali Hage-Hassan

J. Electron. Test., 2005

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Data Retention Fault in SRAM Memories: Analysis and Detection Procedures.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

March iC-: An Improved Version of March C- for ADOFs Detection.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution.

[BibT_eX]

[DOI]

Proceedings of the 9th European Test Symposium, 2004

Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders.

[BibT_eX]

[DOI]