Luigi Dilillo
Orcid: 0000-0002-1295-2688Affiliations:
- LIRMM Montpellier, France
According to our database1,
Luigi Dilillo
authored at least 131 papers
between 2003 and 2024.
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Bibliography
2024
Special Session: Reliability and Performance Evaluation of a RISC-V Vector Extension Unit for Vector Multiplication.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024
Implementation and Reliability Evaluation of a ChaCha20 Stream Cipher Hardware Accelerator.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024
2023
Computer, February, 2023
Proceedings of the 9th International Workshop on Advances in Sensors and Interfaces, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2022
Emulating the Effects of Radiation-Induced Soft-Errors for the Reliability Assessment of Neural Networks.
IEEE Trans. Emerg. Top. Comput., 2022
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design.
Sensors, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
2018
Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
2017
Microelectron. Reliab., 2017
Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics.
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
2015
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
J. Electron. Test., 2014
J. Electron. Test., 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption.
J. Low Power Electron., 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Characterization of an SRAM based particle detector for mixed-field radiation environments.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs.
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability.
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing.
Proceedings of the 22nd Asian Test Symposium, 2013
2012
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC<sup>TM</sup> eFlash Memories.
J. Electron. Test., 2012
J. Electron. Test., 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011
Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench.
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 2011 IEEE International Test Conference, 2011
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
A study of path delay variations in the presence of uncorrelated power and ground supply noise.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.
J. Low Power Electron., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
A two-layer SPICE model of the ATMEL TSTAC<sup>TM</sup> eFlash memory technology for defect injection and faulty behavior prediction.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 15th European Test Symposium, 2010
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
Proceedings of the 2008 IEEE International Test Conference, 2008
2007
J. Electron. Test., 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.
J. Electron. Test., 2006
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.
J. Electron. Test., 2005
J. Electron. Test., 2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization.
Proceedings of the 10th European Test Symposium, 2005
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.
Proceedings of the 42nd Design Automation Conference, 2005
2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Proceedings of the 9th European Test Symposium, 2004
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003