Luciano Volcan Agostini

Orcid: 0000-0002-3421-5830

Affiliations:
  • Federal University of Pelotas, CDTec, Brazil


According to our database1, Luciano Volcan Agostini authored at least 304 papers between 2000 and 2024.

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Bibliography

2024
Memory-Centered Motion Estimation System With CTB-Based Full-Splitting Algorithm.
IEEE Trans. Consumer Electron., May, 2024

Adaptive complexity control for AV1 video encoder using machine learning.
J. Real Time Image Process., May, 2024

A Hardware-Friendly Acceleration of VVC Affine Motion Estimation Using Decision Trees.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

Bit-Width Optimized Transposition Buffer Design for the AV1 2D-DCT Transform.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

A Real-Time UHD 4K Hardware for VVC Affine Linear Equation System Solving.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

A Hardware-Friendly Fast VVC Test Zone Search Algorithm Using Machine Learning.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

Speeding Up the AV1 Global Warped Motion Compensation.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

Coding Efficiency and Time Evaluation of Apple A15 Bionic Chipset HEVC Encoder.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023
Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction.
IEEE Des. Test, October, 2023

Complexity and compression efficiency analysis of libaom AV1 video codec.
J. Real Time Image Process., June, 2023

A High-Throughput Hardware Design for the AV1 Decoder Intraprediction.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Learning-based bypass zone search algorithm for fast motion estimation.
Multim. Tools Appl., 2023

An UHD 4K@120fps Hardware for the VVC Prediction Refinement with Optical Flow.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

4K UHD@60fps Design For The VVC Affine Motion Estimation Reconstructor.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Evaluation of Imprecise Subtractors into Test Zone Search for VVC Encoding.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Hardware Design for the Affine Motion Compensation of the VVC Standard.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

High-Throughput and Multiplierless Hardware Design for the AV1 Fractional Motion Estimation.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

Efficient Architecture for VVC Angular Intra Prediction based on a Hardware-Friendly Heuristic.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

Efficient Hardware Design for the VVC Affine Motion Compensation Exploiting Multiple Constant Multiplication.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Learning-Based Fast VVC Affine Motion Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

High-Throughput Design for a Multi-Size DCT-II Targeting the AV1 Encoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

High-Throughput and Multiplierless Hardware Design for the AV1 Local Warped MC Interpolation.
Proceedings of the IEEE International Conference on Image Processing, 2023

2022
FastInter360: A Fast Inter Mode Decision for HEVC 360 Video Coding.
IEEE Trans. Circuits Syst. Video Technol., 2022

Configurable Fast Block Partitioning for VVC Intra Coding Using Light Gradient Boosting Machine.
IEEE Trans. Circuits Syst. Video Technol., 2022

Quality-power configurable flexible coding order hardware design for real-time 3D-HEVC intra-frame prediction.
J. Real Time Image Process., 2022

Power-Quality Configurable Hardware Design for AV1 Directional Intraframe Prediction.
IEEE Des. Test, 2022

A Learning-Based Framework for Depth Perception using Dense Light Fields.
Proceedings of the WebMedia '22: Brazilian Symposium on Multimedia and Web, Curitiba, Brazil, November 7, 2022

Hardware Design for the Separable Symmetric Normalized Wiener Filter of the AV1 Decoder.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

An UHD 4K@60fps Dual Self-Guided Filter Targeting the AV1 Decoder.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Low-Frequency Non-Separable Transform Hardware System Design for the VVC Encoder.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Direction-Based Fast Mode Decision and Hardware Design for the AV1 Intra Prediction.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Multi-Objective optimized Complexity Control for the AV1 Video Encoder.
Proceedings of the Picture Coding Symposium, 2022

Fast Transform Decision Scheme for VVC Intra-Frame Prediction Using Decision Trees.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A High-Throughput Design for the H.266/VVC Low-Frequency Non-Separable Transform.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Fast Affine Motion Estimation for VVC using Machine-Learning-Based Early Search Termination.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Mode-Adaptive Subsampling of SAD/SSE Operations for Intra Prediction Cost Reduction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

GM-RF: An AV1 Intra-Frame Fast Decision Based on Random Forest.
Proceedings of the 2022 IEEE International Conference on Image Processing, 2022

A Hardware-Friendly and Configurable Heuristic Targeting VVC Inter-Frame Prediction.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

VVC Interpicture Prediction Using SAD with Imprecise Subtractors: A Quantitative Analysis.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Guest Editorial Special Section on IEEE ICECS 2020.
IEEE Open J. Circuits Syst., 2021

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design.
IEEE Open J. Circuits Syst., 2021

Performance analysis of VVC intra coding.
J. Vis. Commun. Image Represent., 2021

Using curved angular intra-frame prediction to improve video coding efficiency.
J. Vis. Commun. Image Represent., 2021

Low-energy motion estimation memory system with dynamic management.
J. Real Time Image Process., 2021

Fast and energy-efficient approximate motion estimation architecture for real-time 4 K UHD processing.
J. Real Time Image Process., 2021

Fast block partitioning scheme for chrominance intra prediction of versatile video coding standard.
J. Electronic Imaging, 2021

Learning-Based Complexity Reduction Scheme for VVC Intra-Frame Prediction.
Proceedings of the International Conference on Visual Communications and Image Processing, 2021

Analysis of VVC Intra Prediction Block Partitioning Structure.
Proceedings of the International Conference on Visual Communications and Image Processing, 2021

SAD or SATD? How the Distortion Metric Impacts a Fractional Motion Estimation VLSI Architecture.
Proceedings of the 23rd International Workshop on Multimedia Signal Processing, 2021

Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video Coding.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Fast 3D-HEVC Depth Map Encoding Using Machine Learning.
IEEE Trans. Circuits Syst. Video Technol., 2020

3D-HEVC Bipartition Modes Encoder and Decoder Design Targeting High-Resolution Videos.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Tile Adaptation for Workload Balancing of 3D-HEVC Encoder in Homogeneous Multicore Systems.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

6WR: A Hardware Friendly 3D-HEVC DMM-1 Algorithm and its Energy-Aware and High-Throughput Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A High-Throughput Hardware Architecture for AV1 Non-Directional Intra Modes.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Complexity and compression efficiency assessment of 3D-HEVC encoder.
Multim. Tools Appl., 2020

Speedup evaluation of HEVC parallel video coding using Tiles.
J. Real Time Image Process., 2020

Parallelism exploration for 3D high-efficiency video coding depth modeling mode one.
J. Real Time Image Process., 2020

UHD 8K energy-quality scalable HEVC intra-prediction SAD unit hardware using optimized and configurable imprecise adders.
J. Real Time Image Process., 2020

High-Throughput Hardware for 3D-HEVC Depth-Map Intra Prediction.
IEEE Des. Test, 2020

Multicore Parallelism Exploration Targeting 3D-HEVC Intra-Frame Prediction.
IEEE Des. Test, 2020

High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
IEEE Des. Test, 2020

4D-DCT Hardware Architecture for JPEG Pleno Light Field Coding.
Proceedings of the 2020 IEEE International Conference on Visual Communications and Image Processing, 2020

ERP-Based CTU Splitting Early Termination for Intra Prediction of 360 videos.
Proceedings of the 2020 IEEE International Conference on Visual Communications and Image Processing, 2020

2PSA: An Optimized and Flexible Power-Precision Scalable Adder.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Directional Intra Frame Prediction Architecture with Edge Filter and Upsampling for AV1 Video Coding.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

A Hardware Design for 3D-HEVC Depth Intra Skip with Synthesized View Distortion Change.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

High-Throughput CDEF Architecture for the AV1 Decoder Targeting 4K@60fps Videos.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

A Low-Complexity Algorithm and Its Low-Power and High-Throughput Architecture for 3D-HEVC DMM-1 Encoding Tool.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Efficient Hardware Design for the AV1 CDEF Filter Targeting 4K UHD Videos.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Fast Partitioning Decision Scheme for Versatile Video Coding Intra-Frame Prediction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

ASIC Solution for the Directional Intra Prediction of the AV1 Encoder Targeting UHD 4K Videos.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Complexity Analysis Of VVC Intra Coding.
Proceedings of the IEEE International Conference on Image Processing, 2020

Memory Assessment Of Versatile Video Coding.
Proceedings of the IEEE International Conference on Image Processing, 2020

An UHD 4K@60fps Deblocking Filter Hardware Targeting the AV1 Decoder.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

An Overview of Dedicated Hardware Designs for State-of-the-Art AV1 and H.266/VVC Video Codecs.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Fast Intra Mode Decision for 3D-HEVC Depth Map Coding using Decision Trees.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Memory Profiling of H.266 Versatile Video Coding Standard.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Spatially Adaptive Intra Mode Pre-Selection for ERP 360 Video Coding.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

ESA360 - Early SKIP Mode Decision Algorithm for Fast ERP 360 Video Coding.
Proceedings of the 28th European Signal Processing Conference, 2020

Fast Block Size Decision for HEVC Encoders with On-the-Fly Trained Classifiers.
Proceedings of the 28th European Signal Processing Conference, 2020

2019
Performance Analysis of Depth Intra-Coding in 3D-HEVC.
IEEE Trans. Circuits Syst. Video Technol., 2019

Energy-Aware Motion and Disparity Estimation System for 3D-HEVC With Run-Time Adaptive Memory Hierarchy.
IEEE Trans. Circuits Syst. Video Technol., 2019

Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation Reuse.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

High-Throughput Multifilter Interpolation Architecture for AV1 Motion Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Quality and Energy-Aware HEVC Transrating Based on Machine Learning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Analysis of parallel encoding using tiles in 3D High Efficiency Video Coding.
Signal Image Video Process., 2019

Efficient reference frame compression scheme for video coding systems: algorithm and VLSI design.
J. Real Time Image Process., 2019

High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator.
J. Real Time Image Process., 2019

Fast partitioning decision making for prediction units on H.264-to-HEVC transcoding using machine learning.
Proceedings of the 25th Brazillian Symposium on Multimedia and the Web, 2019

A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Hardware design of DC/CFL intra-prediction decoder for the AV1 codec.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

IPBN: alerts management in intravenous electromedical devices using bayesian networks.
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Low-Power and High-Throughput Approximate 4×4 DCT Hardware Architecture.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

A High Throughput Hardware Architecture Targeting the AV1 Paeth Intra Predictor.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

TITAN: Tile Timing-Aware Balancing Algorithm for Speeding Up the 3D-HEVC Intra Coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

High Throughput Hardware Design for AV1 Paeth and Smooth Intra Modes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Encoding Efficiency and Computational Cost Assessment of State-Of-The-Art Point Cloud Codecs.
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

Energy-Efficiency Exploration of Memory Hierarchy using NVMs for HEVC Motion Estimation.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A New Hardware Friendly 2D-DCT HEVC Compliant Algorithm and its High Throughput and Low Power Hardware Design.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A Fast Local Mode Decision for the HEVC Intra Prediction Based on Direction Detection.
Proceedings of the 27th European Signal Processing Conference, 2019

Complexity Scalable HEVC-to-AV1 Transcoding Based on Coding Tree Depth Inheritance.
Proceedings of the 27th European Signal Processing Conference, 2019

Compression Efficiency and Computational Cost Comparison between AV1 and HEVC Encoders.
Proceedings of the 27th European Signal Processing Conference, 2019

FastIntra360: A Fast Intra-Prediction Technique for 360-Degrees Video Coding.
Proceedings of the Data Compression Conference, 2019

Online Machine Learning for Fast Coding Unit Decisions in HEVC.
Proceedings of the Data Compression Conference, 2019

2018
A reduced computational effort mode-level scheme for 3D-HEVC depth maps intra-frame prediction.
J. Vis. Commun. Image Represent., 2018

Reference frame context-adaptive variable-length coder: a real-time hardware-friendly approach for lossless external memory bandwidth reduction in current video-coding systems.
J. Real Time Image Process., 2018

Low-Power and High-Throughput Architecture for 3D-HEVC Depth Modeling Mode 4.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Hardware-Oriented Wedgelet Evaluation Skip for DMM-1 in 3D-HEVC.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

3D-HEVC DMM-1 Parallelism Exploration Targeting Multicore Systems.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

High Throughput Multiplierless Architecture for VP9 Fractional Motion Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Low-Power HEVC 1-D IDCT Hardware Architecture.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

ASIC power-estimation accuracy evaluation: A case study using video-coding architectures.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Fast and energy-efficient HEVC transrating based on frame partitioning inheritance.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Coding- and Energy-Efficient FME Hardware Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

High Efficient Architecture for 3D-HEVC DMM-1 Decoder Targeting 1080p Videos.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Configurable Cache Memory Architecture for Low-Energy Motion Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Hardware-Friendly Unidirectional Disparity-Search Algorithm for 3D-HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

DCDM-Intra: Dynamically Configurable 3D-HEVC Depth Maps Intra-Frame Prediction Algorithm.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

LF-CAE: Context-Adaptive Encoding for Lenslet Light Fields Using HEVC.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

Memory-Aware Tiles Workload Balance through Machine-Learnt Complexity Reduction for HEVC.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Low Area Reconfigurable Architecture for 3D-HEVC DMMs Decoder Targeting 1080p Videos.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Least-Squares Approximation Surfaces for High Quality Intra-Frame Prediction in Future Video Standards.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Fast 3D-Hevc Depth Maps Intra-Frame Prediction Using Data Mining.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Octagonal-Axis Raster Pattern for Improved Test Zone Search Motion Estimation.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Intravenous Electromedical Equipment: A Proposal to Improve Accuracy in Generating Alerts.
Proceedings of the XLIV Latin American Computer Conference, 2018

2017
Real-time scalable hardware architecture for 3D-HEVC bipartition modes.
J. Real Time Image Process., 2017

Energy-aware scheme for the 3D-HEVC depth maps prediction.
J. Real Time Image Process., 2017

Rate and Complexity-Aware Coding Scheme for Fixed-Camera Videos Based on Region-of-Interest Detection.
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017

Cache Memory Energy Efficiency Exploration for the HEVC Motion Estimation.
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017

Low-area scalable hardware architecture for DMM-1 encoder of 3D-HEVC video coding standard.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Energy-efficient motion estimation with approximate arithmetic.
Proceedings of the 19th IEEE International Workshop on Multimedia Signal Processing, 2017

Multiple early-termination scheme for TZ search algorithm based on data mining and decision trees.
Proceedings of the 19th IEEE International Workshop on Multimedia Signal Processing, 2017

Characterizing energy consumption in software HEVC encoders: HM vs x265.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Energy evaluation of the HEVC decoding for different encoding configurations.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Complexity reduction by modes reduction in RD-list for intra-frame prediction in 3D-HEVC depth maps.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

High-throughput HEVC intrapicture prediction hardware design targeting UHD 8K videos.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A multiplierless parallel HEVC quantization hardware for real-time UHD 8K video coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Low-power and high-throughput hardware design for the 3D-HEVC depth intra skip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Edge-aware depth motion estimation - A complexity reduction scheme for 3D-HEVC.
Proceedings of the 25th European Signal Processing Conference, 2017

Depth modeling modes complexity control system for the 3D-HEVC video encoder.
Proceedings of the 25th European Signal Processing Conference, 2017

Complexity reduction of 3D-HEVC based on depth analysis for background and ROI classification.
Proceedings of the 25th European Signal Processing Conference, 2017

2016
Pareto-Based Method for High Efficiency Video Coding With Limited Encoding Time.
IEEE Trans. Circuits Syst. Video Technol., 2016

Fast intra prediction algorithm based on texture analysis for 3D-HEVC encoders.
J. Real Time Image Process., 2016

Complexity scalability for real-time HEVC encoders.
J. Real Time Image Process., 2016

DFPS: a fast pattern selector for depth modeling mode 1 in three-dimensional high-efficiency video coding standard.
J. Electronic Imaging, 2016

Energy-aware light-weight DMM-1 patterns decoders with efficiently storage in 3D-HEVC.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A parallel Motion Estimation solution for heterogeneous System on Chip.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Squarer exploration for energy-efficient sum of squared differences.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Solutions for DMM-1 complexity reduction in 3D-HEVC based on gradient calculation.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Energy analisys of motion estimation memory transference on embedded processors.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Rate-distortion-complexity analysis for prediction unit modes in 3D-HEVC depth coding.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Energy-efficient SATD for beyond HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An HEVC multi-size DCT hardware with constant throughput and supporting heterogeneous CUs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Fast H.264/AVC to HEVC transcoder based on data mining and decision trees.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Speedup-aware history-based tiling algorithm for the HEVC standard.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Rate-constrained successive elimination of Hadamard-based SATDs.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Pareto-based energy control for the HEVC encoder.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

An efficient sub-sample interpolator hardware for VP9-10 standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Complexity reduction for 3D-HEVC depth map coding based on early Skip and early DIS scheme.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Coarse grain partial distortion elimination for Hadamard ME in HEVC.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Real-time simplified edge detector architecture for 3D-HEVC depth maps coding.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

3D-HEVC depth maps intra prediction complexity analysis.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Fast HEVC Encoding Decisions Using Data Mining.
IEEE Trans. Circuits Syst. Video Technol., 2015

DMMFast: a complexity reduction scheme for three-dimensional high-efficiency video coding intraframe depth map coding.
J. Electronic Imaging, 2015

Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A Low-Area and High-Throughput Intra Prediction Architecture for a Multi-Standard HEVC and H.264/AVC Video Encoder.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Memory-Aware and High-Throughput Hardware Design for the HEVC Fractional Motion Estimation.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

S-GMOF: A gradient-based complexity reduction algorithm for depth-maps intra prediction on 3D-HEVC.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A multi-standard interpolation filter for motion compensated prediction on high definition videos.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Hardware design of fast HEVC 2-D IDCT targeting real-time UHD 4K applications.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A real-time architecture for reference frame compression for high definition video coders.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Complexity reduction for the 3D-HEVC depth maps coding.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Encoding time control system for HEVC based on Rate-Distortion-Complexity analysis.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fast mode selection algorithm based on texture analysis for 3D-HEVC intra prediction.
Proceedings of the 2015 IEEE International Conference on Multimedia and Expo, 2015

A multi-standard interpolation hardware solution for H.264 and HEVC.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

2014
Inter-view prediction of intra mode decision for high-efficiency video coding-based multiview video coding.
J. Electronic Imaging, 2014

Complexity reduction of depth intra coding for 3D video extension of HEVC.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

A complexity reduction algorithm for depth maps intra prediction on the 3D-HEVC.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

Sample adaptive offset filter hardware design for HEVC encoder.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

Four-step algorithm for early termination in HEVC inter-frame prediction based on decision trees.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

A Real-Time 5-Views HD 1080p Architecture for 3D-HEVC Depth Modeling Mode 4.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

A Memory Energy Consumption Analysis of Motion Estimation Algorithms using Data Reuse in Video Coding Systems.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

An efficient reference frame compression approach for video coding systems.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

HEVC Fractional Motion Estimation complexity reduction for real-time applications.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Configurable hardware design for the HEVC-based Adaptive Loop Filter.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Overview and quality analysis in 3D-HEVC emergent video coding standard.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Memory energy consumption reduction in video coding systems.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Memory bandwidth reduction for H.264 and HEVC encoders using lossless reference frame coding.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Power efficient and high troughtput multi-size IDCT targeting UHD HEVC decoders.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A new differential and lossless Reference Frame Variable-Length Coder: An approach for high definition video coders.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Complexity reduction for 3D-HEVC depth maps intra-frame prediction using simplified edge detector algorithm.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Classification-based early termination for coding tree structure decision in HEVC.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A low-complexity and lossless reference frame encoder algorithm for video coding.
Proceedings of the IEEE International Conference on Acoustics, 2014

Cost function optimization and its hardware design for the Sample Adaptive Offset of HEVC standard.
Proceedings of the 22nd European Signal Processing Conference, 2014

A method for early-splitting of HEVC inter blocks based on decision trees.
Proceedings of the 22nd European Signal Processing Conference, 2014

2013
Iterative random search: a new local minima resistant algorithm for motion estimation in high-definition videos.
Multim. Tools Appl., 2013

A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4: 2: 2 profile.
J. Real Time Image Process., 2013

Hardware design for the 32×32 IDCT of the HEVC video coding standard.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

HEVC intra mode decision acceleration based on tree depth levels relationship.
Proceedings of the 30th Picture Coding Symposium, 2013

Fast HEVC intra mode decision algorithm based on new evaluation order in the Coding Tree Block.
Proceedings of the 30th Picture Coding Symposium, 2013

Constrained encoding structures for computational complexity scalability in HEVC.
Proceedings of the 30th Picture Coding Symposium, 2013

A real time high definition architecture for the Variable-Length Reference Frame Decoder.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

A fast hardware-friendly motion estimation algorithm and its VLSI design for real time ultra high definition applications.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Low cost and high throughput FME interpolation for the HEVC emerging video coding standard.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

A lossless approach for external memory bandwidth reduction in video coding systems and its VLSI architecture.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo, 2013

A hardware friedly motion estimation algorithm for the emergent HEVC standard and its low power hardware design.
Proceedings of the IEEE International Conference on Image Processing, 2013

Content-adaptive reference frame compression based on intra-frame prediction for multiview video coding.
Proceedings of the IEEE International Conference on Image Processing, 2013

An adaptive workload management scheme for HEVC encoding.
Proceedings of the IEEE International Conference on Image Processing, 2013

An energy-efficient hardware design for lossless reference frame compression in video coders.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Inter-view prediction of coding tree depth for HEVC-based multiview video coding.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

ES&IS: Enhanced Spread and Iterative Search hardware-friendly motion estimation algorithm for the HEVC Standard.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

High throughput hardware design for the HEVC Fractional Motion Estimation Interpolation Unit.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Computational complexity control for HEVC based on coding tree spatio-temporal correlation.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Speeding up HEVC intra coding based on tree depth inter-levels correlation structure.
Proceedings of the 21st European Signal Processing Conference, 2013

Complexity control of HEVC through quadtree depth estimation.
Proceedings of Eurocon 2013, 2013

Coding Tree Depth Estimation for Complexity Reduction of HEVC.
Proceedings of the 2013 Data Compression Conference, 2013

Simplified HEVC FME Interpolation Unit Targeting a Low Cost and High Throughput Hardware Design.
Proceedings of the 2013 Data Compression Conference, 2013

Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder.
VLSI Design, 2012

Performance and Computational Complexity Assessment of High-Efficiency Video Encoders.
IEEE Trans. Circuits Syst. Video Technol., 2012

Evaluating two implementations of the component responsible for decoding video and audio in the Brazilian digital TV middleware.
Multim. Tools Appl., 2012

DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation.
Int. J. Reconfigurable Comput., 2012

Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders.
Int. J. Reconfigurable Comput., 2012

A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos.
Int. J. Reconfigurable Comput., 2012

Performance and Energy Consumption Analysis of Embedded Applications Based on Android Platform.
Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

High throughput hardware design for the Adaptive Loop Filter of the emerging HEVC video coding.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Adaptive coding tree for complexity control of high efficiency video encoders.
Proceedings of the 2012 Picture Coding Symposium, 2012

Spread and Iterative Search: A High Quality Motion Estimation Algorithm for High Definition Videos and Its VLSI Design.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

Motion Vectors Merging: Low Complexity Prediction Unit Decision Heuristic for the Inter-prediction of HEVC Encoders.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

High performance hardware architectures for the inverse Rotational Transform of the emerging HEVC standard.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

Motion compensated tree depth limitation for complexity control of HEVC encoding.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

Fast HEVC intra mode decision based on dominant edge evaluation and tree structure dependencies.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A high quality hardware friendly motion estimation algorithm focusing in HD videos.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Dynamic tree-depth adjustment for low power HEVC encoders.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Fast HEVC intra prediction mode decision based on EDGE direction information.
Proceedings of the 20th European Signal Processing Conference, 2012

2011
Complexity control of high efficiency video encoders for power-constrained devices.
IEEE Trans. Consumer Electron., 2011

A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos.
Int. J. Reconfigurable Comput., 2011

A comparative analysis of media processing component implementations for the Brazilian digital TV middleware.
Int. J. Inf. Technol. Commun. Convergence, 2011

Two fast multi-point search algorithms for high quality motion estimation in high resolution videos.
Int. J. Inf. Technol. Commun. Convergence, 2011

Two Novel Algorithms for High Quality Motion Estimation in High Definition Video Sequences.
Proceedings of the 24th SIBGRAPI Conference on Graphics, 2011

An efficient ME architecture for high definition videos using the new MPDS algorithm.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

An efficient memory hierarchy for full search motion estimation on high definition digital videos.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Tests and Performance Analysis of Media Processing Implementations for the Middleware of Brazilian Digital TV System Using Different Scenarios.
Proceedings of the 5th FTRA International Conference on Multimedia and Ubiquitous Engineering, 2011

A multilevel data reuse scheme for Motion Estimation and its VLSI design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A high throughput H.264/AVC intra-frame encoding loop architecture for HD1080p.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

SHBS: A heuristic for fast inter mode decision of H.264/AVC standard targeting VLSI design.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A real time HDTV motion estimation architecture for the new MPDS algorithm.
Proceedings of EUROCON 2011, 2011

Run-time adaptive energy-aware motion and disparity estimation in multiview video coding.
Proceedings of the 48th Design Automation Conference, 2011

2010
High Throughput and Low Cost Architecture for the Forward Quantization of the H.264/AVC Video Compression Standard.
CLEI Electron. J., 2010

Timing and interface communication analysis of H.264/AVC encoder using SystemC model.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A novel macroblock-level filtering upsampling architecture for H.264/AVC scalable extension.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Variable block size motion estimation architecture with a fast bottom-up decision mode and an integrated motion compensation targeting the H.264/AVC video coding standard.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

A high performance hardware architecture for the H.264/AVC half-pixel motion estimation refinement.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Memory-aware multiple reference frame motion estimation for the H.264/AVC standard.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Homogeneity and distortion-based intra mode decision architecture for H.264/AVC.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Design of an interlayer deblocking filter architecture for H.264/SVC based on a novel sample-level filtering order.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Transforms and quantization design targeting the H.264/AVC intra prediction constraints.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Low latency and high throughput dedicated loop of transforms and quantization focusing in the H.264/AVC Intra Prediction.
Proceedings of the International Conference on Image Processing, 2009

High throughput scalable Motion Compensation architecture for H.264/SVC video coding standard.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A multitransform architecture for the H.264/AVC standard and its design space exploration.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A high throughput and low cost diamond search architecture for HDTV motion estimation.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

2007
Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs.
Microprocess. Microsystems, 2007

Design and FPGA Prototyping of a H.264/AVC Main Profile.
J. Braz. Comput. Soc., 2007

FPGA Prototyping Strategy for a H.264/AVC Video Decoder.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Motion Compensation Hardware Accelerator Architecture for H.264/AVC.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

High Throughput Hardware Architecture for Motion Estimation with 4: 1 Pel Subsampling Targeting Digital Television Applications.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High Throughput Architecture for Forward Transforms Module of H.264/AVC Video Coding Standard.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

RIC Fast Adder and its Set Tolerant Implementation in FPGAs.
Proceedings of the FPL 2007, 2007

2006
Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV.
Proceedings of the IFIP VLSI-SoC 2006, 2006

High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High Throughput Architecture of JPEG Compressor for Color Images Targeting FPGAs.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

High throughput architecture for H.264/AVC forward transforms block.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

FPGA Based Architectures for H. 264/AVC Video Compression Standard.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA Design of A H.264/AVC Main Profile Decoder for HDTV.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
Parallel color space converters for JPEG image compression.
Microelectron. Reliab., 2004

Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation.
Proceedings of the 2004 Design, 2004

2002
Pipelined Entropy Coders for JPEG Compression.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

2001
Pipelined Fast 2-D DCT Architecture for JPEG Image Compression.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

2000
SisECO: Design of an Echo-Canceling IC for Base Band Modems.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Using Reconfigurability Features to Break Down Test Costs: a Case Study.
Proceedings of the 1st Latin American Test Workshop, 2000


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