Lucas Moura Santana

According to our database, Lucas Moura Santana authored at least 6 papers between 2018 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS.

Lucas Moura Santana, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS.

Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx

IEEE J. Solid State Circuits, 2022

2021

A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC.

Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx

Proceedings of the 47th ESSCIRC 2021, 2021

2018

FPGA implementation of high-performance asynchronous pipelines with robust control.

Duarte Lopes de Oliveira, Kledermon Garcia, Lucas Moura Santana, Lester de Abreu Faria

Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

A novel state assignment method for XBM AFSMs without the essential hazard assumption.

Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lucas Moura Santana, Lester de Abreu Faria

Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption.

Higor A. Delsoto, Duarte Lopes de Oliveira, Lucas Moura Santana, Lester de Abreu Faria

Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018