Lucas A. Tambara

Proceedings of the IEEE International Conference on Design, 2024

2023

Notched gate MOSFET for capacitance reduction in RF SOI technology.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE International Conference on Design, 2023

2019

Experimental Applications on SRAM-Based FPGA for the NanosatC-BR2 Scientific Mission.

[BibT_eX]

[DOI]

João Baptista dos Santos Martins

Carlos Alberto Zaffari

Otávio Santos Cupertino Durão

Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2017

Analyzing the impact of radiation-induced failures in flash-based APSoC with and without fault tolerance techniques at CERN environment.

[BibT_eX]

[DOI]

Eduardo Chielle

Georgios Tsiligiannis

Salvatore Danzeca

Markus Brugger

A. Masi

Microelectron. Reliab., 2017

Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs.

[BibT_eX]

[DOI]

André Santos

Microprocess. Microsystems, 2017

Evaluating the efficiency of using TMR in the high-level synthesis design flow of SRAM-based FPGA.

[BibT_eX]

[DOI]

André Flores dos Santos

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Applying lockstep in dual-core ARM Cortex-A9 to mitigate radiation-induced soft errors.

[BibT_eX]

[DOI]

Ádria Barros de Oliveira

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs.

[BibT_eX]

[DOI]

André Flores dos Santos

Fabio Benevenuti

Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC.

[BibT_eX]

[DOI]

Ádria Barros de Oliveira

Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016

Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors.

[BibT_eX]

[DOI]

Fernanda Gusmão de Lima Kastensmidt

André Flores dos Santos

Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015

Exploring design diversity redundancy to improve resilience in mixed-signal systems.

[BibT_eX]

[DOI]

Cristiano P. Chenet

Gabriel de M. Borges

Marcelo Soares Lubaszewski

Tiago R. Balen

Microelectron. Reliab., 2015

Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments.

[BibT_eX]

[DOI]

Jimmy Tarrillo

Ricardo Reis

Proceedings of the 16th Latin-American Test Symposium, 2015

Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects.

[BibT_eX]

[DOI]

Felipe Almeida

Paolo Rech

Fernanda Gusmão de Lima Kastensmidt

Giovanni Bruni

Christopher Frost

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014

Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity.

[BibT_eX]

[DOI]

Ricardo Reis

Alessandro Paccagnella

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects.

[BibT_eX]

[DOI]

Ricardo Reis

Evaldo Carlos Fonseca Pereira

Rafael Galhardo Vaz

Odair Lelis Goncalez

Proceedings of the 15th Latin American Test Workshop, 2014

Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs.

[BibT_eX]

[DOI]

Paolo Rech

Christopher Frost

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC.

[BibT_eX]

[DOI]