Lucas A. Tambara

Orcid: 0009-0000-3917-1366

According to our database1, Lucas A. Tambara authored at least 17 papers between 2013 and 2024.

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Bibliography

2024
MOSFET electron mobility enhancement using source/drain recess.
Proceedings of the IEEE International Conference on Design, 2024

2023
Notched gate MOSFET for capacitance reduction in RF SOI technology.
Proceedings of the 2023 IEEE International Conference on Design, 2023

2019
Experimental Applications on SRAM-Based FPGA for the NanosatC-BR2 Scientific Mission.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2017
Analyzing the impact of radiation-induced failures in flash-based APSoC with and without fault tolerance techniques at CERN environment.
Microelectron. Reliab., 2017

Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs.
Microprocess. Microsystems, 2017

Evaluating the efficiency of using TMR in the high-level synthesis design flow of SRAM-based FPGA.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Applying lockstep in dual-core ARM Cortex-A9 to mitigate radiation-induced soft errors.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Exploring design diversity redundancy to improve resilience in mixed-signal systems.
Microelectron. Reliab., 2015

Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments.
Proceedings of the 16th Latin-American Test Symposium, 2015

Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects.
Proceedings of the 15th Latin American Test Workshop, 2014

Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013


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