Luca Sterpone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

ZOR: Zero Overhead Reliability Strategies for AI Accelerators.

[BibT_eX]

[DOI]

Eleonora Vacca

Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

On the Fault Tolerance of Self-Supervised Training in Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

A New Reliability Analysis of RISC-V Soft Processor for Safety-Critical Systems.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

Assessment of RISC-V Processor Suitability for Satellite Applications.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

Scalable K-Nearest Neighbors Implementation using Distributed Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

A Novel Robust Core for Detecting Node Failures in FPGA Clusters.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2023

Fighting for a future free from violence: A framework for real-time detection of "Signal for Help".

[BibT_eX]

[DOI]

Intell. Syst. Appl., 2023

High-Performance SET Hardening Technique for Vision-Oriented Applications.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Synthesis, 2023

PyXEL: Exploring Bitstream Analysis to Assess and Enhance the Robustness of Designs on FPGAs.

[BibT_eX]

[DOI]

Filomena Decuzzi

Proceedings of the 19th International Conference on Synthesis, 2023

Enhanced Video Surveillance Systems for "Signal for Help" Detection on Edge Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Technology and Society, 2023

Design Techniques for Multi-Core Neural Network Accelerators on Radiation-Hardened FPGAs.

[BibT_eX]

[DOI]

Andrea Portaluri

Proceedings of the 22nd International Symposium on Parallel and Distributed Computing, 2023

RunSAFER: A Novel Runtime Fault Detection Approach for Systolic Array Accelerators.

[BibT_eX]

[DOI]

Eleonora Vacca

Giorgio Ajmone

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Programmable SEL Test Monitoring System for Radiation Hardness Assurance.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

A Comprehensive Analysis of Transient Errors on Systolic Arrays.

[BibT_eX]

[DOI]

Eleonora Vacca

Salvatore Gabriele La Greca

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications.

[BibT_eX]

[DOI]

Stephen King

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Framework for Uniformly Analyze and Mitigate Radiation-effects on FPGAs for Aerospace.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

Reliability Analysis of Microarchitectural Faults in GPGPU-based HPC Systems.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

Assessing the Robustness of Real-Time Operating System on Soft Processor against Multiple Bit Upset.

[BibT_eX]

[DOI]

Andrea Portaluri

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022

Evaluating low-level software-based hardening techniques for configurable GPU architectures.

[BibT_eX]

[DOI]

Marcio M. Gonçalves

José Rodrigo Azambuja

J. Supercomput., 2022

FireNN: Neural Networks Reliability Evaluation on Hybrid Platforms.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

An Automated Continuous Integration Multitest Platform for Automotive Systems.

[BibT_eX]

[DOI]

IEEE Syst. J., 2022

A Placement-Oriented Mitigation Technique for Single Event Effect in Monolithic 3D IC.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Synthesis, 2022

Analysis and Mitigation of Soft-Errors on High Performance Embedded GPUs.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Parallel and Distributed Computing, 2022

Radiation-induced Effects on DMA Data Transfer in Reconfigurable Devices.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Test, Reliability and Functional Safety Trends for Automotive System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded Process.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

On the Reliability of Real-Time Operating System on Embedded Soft Processor for Space Applications.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - 35th International Conference, 2022

2021

A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability.

[BibT_eX]

[DOI]

Pierpaolo Narducci

J. Supercomput., 2021

On the Evaluation of SEEs on Open-Source Embedded Static RAMs.

[BibT_eX]

[DOI]

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Design and Mitigation Techniques of Radiation Induced SEEs on Open-Source Embedded Static RAMs.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

A New Domains-based Isolation Design Flow for Reconfigurable SoCs.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

A Neutron Generator Testing Platform for the Radiation Analysis of SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2021

SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft Processor.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs.

[BibT_eX]

[DOI]

IEEE Access, 2020

A dynamic reconfiguration mechanism to increase the reliability of GPGPUs.

[BibT_eX]

[DOI]

Pierpaolo Narducci

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

A New Single Event Transient Hardened Floating Gate Configurable Logic Circuit.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU.

[BibT_eX]

[DOI]

Marcio Gonçalves

José Rodrigo Azambuja

Proceedings of the IEEE Latin-American Test Symposium, 2020

Digital Design Techniques for Dependable High Performance Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets.

[BibT_eX]

[DOI]

Marcio Gonçalves

José Rodrigo Azambuja

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

An Emulation Platform for Evaluating the Reliability of Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs.

[BibT_eX]

[DOI]

Pierpaolo Narducci

Heinrich Theodor Vierhaus

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

On the Evaluation of SEU Effects on AXI Interconnect Within AP-SoCs.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020

Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019

A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs.

[BibT_eX]

[DOI]

Raoul Grimoldi

L. Cattaneo

Integr., 2019

Analyzing Radiation-Induced Transient Errors on SRAM-Based FPGAs by Propagation of Broadening Effect.

[BibT_eX]

[DOI]

IEEE Access, 2019

A new Method for the Analysis of Radiation-induced Effects in 3D VLSI Face-to-Back LUTs.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Synthesis, 2019

On the evaluation of SEU effects in GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin American Test Symposium, 2019

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

On the Evaluation of the PIPB Effect within SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE European Test Symposium, 2019

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018

OLT(RE)<sup>2</sup>: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2018

On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs.

[BibT_eX]

[DOI]

L. Cattaneo

Proceedings of the 15th International Conference on Synthesis, 2018

PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

About the functional test of the GPGPU scheduler.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

On the mitigation of single event transients on flash-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE European Test Symposium, 2018

MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2017

An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

A new approach for Total Ionizing Dose effect analysis on Flash-based FPGA.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2017

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2017

A probe-based SEU detection method for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Luca Boragno

Microelectron. Reliab., 2017

A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs.

[BibT_eX]

[DOI]

J. Syst. Archit., 2017

Evaluation of transient errors in GPGPUs for safety critical applications: An effective simulation-based fault injection environment.

[BibT_eX]

[DOI]

J. Syst. Archit., 2017

Fault tolerant electronic system design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2017

Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Reliability evaluation of heterogeneous systems-on-chip for automotive ECUs.

[BibT_eX]

[DOI]

Annarita Moramarco

Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017

Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs.

[BibT_eX]

[DOI]

Luca Boragno

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Online monitoring soft errors in reconfigurable FPGA during radiation test.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2017

Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs.

[BibT_eX]

[DOI]

Raoul Grimoldi

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Self rerouting of dynamically reconfigurable SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017

2016

Online Test of Control Flow Errors: A New Debug Interface-Based Approach.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

On the prediction of radiation-induced SETs in flash-based FPGAs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

UA<sup>2</sup>TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs.

[BibT_eX]

[DOI]

Integr., 2016

An FPGA-based testing platform for the validation of automotive powertrain ECU.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Analysis of radiation-induced SEUs on dynamic reconfigurable systems.

[BibT_eX]

[DOI]

Luca Boragno

Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Hybrid soft error mitigation techniques for COTS processor-based systems.

[BibT_eX]

[DOI]

Eduardo Chielle

Sergio Cuenca-Asensi

Proceedings of the 17th Latin-American Test Symposium, 2016

Scalable FPGA graph model to detect routing faults.

[BibT_eX]

[DOI]

Sebastiano F. Finocchiaro

Gianpiero Cabodi

Carmelo Loiacono

Francesco Savarese

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

A New Simulation-Based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015

Radiation-induced single event transients modeling and testing on nanometric flash-based technologies.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2015

On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs.

[BibT_eX]

[DOI]

Lorenzo Venditti

Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014

On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs.

[BibT_eX]

[DOI]

J. Electron. Test., 2014

Soft error effects analysis and mitigation in VLIW safety-critical applications.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

A new solution to on-line detection of Control Flow Errors.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs.

[BibT_eX]

[DOI]

Marco Desogus

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Fault injection in GPGPU cores to validate and debug robust parallel applications.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs.

[BibT_eX]

[DOI]

Ernesto Sánchez

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Analysis and mitigation of single event effects on flash-based FPGAS.

[BibT_eX]

[DOI]

Heinrich Theodor Vierhaus

Proceedings of the 19th IEEE European Test Symposium, 2014

Reconfigurable high performance architectures: How much are they ready for safety-critical applications?

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation.

[BibT_eX]

[DOI]

Dan Alexandrescu

Celia López-Ongil

Proceedings of the 19th IEEE European Test Symposium, 2014

2013

A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing.

[BibT_eX]

[DOI]

Mario Porrmann

Jens Hagemeyer

IEEE Trans. Computers, 2013

SEL-UP: A CAD tool for the sensitivity analysis of radiation-induced Single Event Latch-Up.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2013

Partition-Based Faults Diagnosis of a VLIW Processor.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

On the development of diagnostic test programs for VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Exploiting the debug interface to support on-line test of control flow errors.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

On the evaluation of soft-errors detection techniques for GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 8th International Design and Test Symposium, 2013

Validation and robustness assessment of an automotive system.

[BibT_eX]

[DOI]

Proceedings of the 8th International Design and Test Symposium, 2013

Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

On-line testing of permanent radiation effects in reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture.

[BibT_eX]

[DOI]

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

Preface.

[BibT_eX]

[DOI]

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

On the optimized generation of Software-Based Self-Test programs for VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A New Fault Injection Approach for Testing Network-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the 20th Euromicro International Conference on Parallel, 2012

On the development of Software-Based Self-Test methods for VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.

[BibT_eX]

[DOI]

Alessandro Paccagnella

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

A new SBST algorithm for testing the register file of VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A scalable platform for run-time reconfigurable satellite payload processing.

[BibT_eX]

[DOI]

Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011

Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs.

[BibT_eX]

[DOI]

Hipólito Guzmán-Miranda

Miguel A. Aguirre

Manuel Gutiérrez-Rizo

IEEE Trans. Ind. Electron., 2011

A Low-Cost Emulation System for Fast Co-verification and Debug.

[BibT_eX]

[DOI]

Jorge Luis Lagos-Benites

Proceedings of the 16th European Test Symposium, 2011

Fault injection analysis of transient faults in clustered VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Analysis of SEU effects in partially reconfigurable SoPCs.

[BibT_eX]

[DOI]

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications.

[BibT_eX]

[DOI]

Springer, ISBN: 978-1-4419-7594-2, 2011

2010

A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2010

A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A novel scalable and reconfigurable emulation platform for embedded systems verification.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An integrated flow for the design of hardened circuits on SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

A New Soft-Error Resilient Voltage-Mode Quaternary Latch.

[BibT_eX]

[DOI]

Eduardo Luis Rhod

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

On the mitigation of SET broadening effects in integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Electronics System Design Techniques for Safety Critical Applications

[BibT_eX]

[DOI]

Lecture Notes in Electrical Engineering 26, Springer, ISBN: 978-1-4020-8978-7, 2009

A Novel Dual-Core Architecture for the Analysis of DNA Microarray Images.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2009

A new RC design for mixed-grain based dynamically reconfigurable architectures.

[BibT_eX]

[DOI]

Eduardo Luis Rhod

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Soft errors in Flash-based FPGAs: Analysis methodologies and first results.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs.

[BibT_eX]

[DOI]

Francesco Abate

Proceedings of the Design, Automation and Test in Europe, 2009

Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2009

2008

FPGA PAL Design Tools.

[BibT_eX]

[DOI]

Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

Software and Hardware Techniques for SEU Detection in IP Processors.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs.

[BibT_eX]

[DOI]

Simone Gerardin

Andrea Manuzzato

Alessandro Paccagnella

Sana Rezgui

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications.

[BibT_eX]

[DOI]

M. A. Aguirre

Jonathan Noel Tombs

Hipólito Guzmán-Miranda

Proceedings of the Design, Automation and Test in Europe, 2008

A graph-based representation of Gene Expression profiles in DNA microarrays.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2008

A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices.

[BibT_eX]

[DOI]

Proceedings of the 5th Conference on Computing Frontiers, 2008

Differential gene expression graphs: A data structure for classification in DNA microarrays.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International Conference on Bioinformatics and Bioengineering, 2008

A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's.

[BibT_eX]

[DOI]

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.

[BibT_eX]

[DOI]

Salvatore Pontarelli

Gian Carlo Cardarilli

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

A new hardware architecture for performing the gridding of DNA microarray images.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A new decompression system for the configuration process of SRAM-based FPGAS.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 12th European Test Symposium, 2007

Optimization of Self Checking FIR filters by means of Fault Injection Analysis.

[BibT_eX]

[DOI]

Salvatore Pontarelli

Gian Carlo Cardarilli

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Andrea Manuzzato

Paolo Rech

Simone Gerardin

Alessandro Paccagnella

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Hardening FPGA-based Systems Against SEUs: A New Design Methodology.

[BibT_eX]

[DOI]

J. Comput., 2006

A Fault Injection Environment for SoPC's Embedded Microprocessors.

[BibT_eX]

Proceedings of the 7th Latin American Test Workshop, 2006

Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Fault Injection-based Reliability Evaluation of SoPCs.

[BibT_eX]

[DOI]

Proceedings of the 11th European Test Symposium, 2006

Combined software and hardware techniques for the design of reliable IP processors.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

A new approach to compress the configuration information of programmable devices.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005

Efficient Estimation of SEU Effects in SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

New evolutionary techniques for test-program generation for complex microprocessor cores.

[BibT_eX]

[DOI]

Ernesto Sánchez

Massimiliano Schillaci

Proceedings of the Genetic and Evolutionary Computation Conference, 2005

Multiple errors produced by single upsets in FPGA configuration memory: a possible solution.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

A design flow for protecting FPGA-based systems against single event upsets.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs.

[BibT_eX]

[DOI]