Luca Selmi
Orcid: 0000-0001-8688-4326
According to our database1,
Luca Selmi
authored at least 32 papers
between 1990 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2015, "For research on carrier transport and reliability of semiconductor devices".
Timeline
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On csauthors.net:
Bibliography
2024
From Finite Element Simulations to Equivalent Circuit Models of Extracellular Neuronal Recording Systems Based on Planar and Mushroom Electrodes.
IEEE Trans. Biomed. Eng., April, 2024
Machine learning and data augmentation methods for multispectral capacitance images of nanoparticles with nanoelectrodes array biosensors.
Eng. Appl. Artif. Intell., January, 2024
2023
Mitigation of Electrical/Ionic Interference in Iontronic Neurostimulation/Neurosensing Platforms: A Simulation Study.
Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023
Identification of Axon Bendings in Neurons by Multiphysics FEM Simulations of High-Density MEA Extracellular Recordings.
Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023
2022
Multiphysics Finite-Element Modeling of the Neuron/Electrode Electrodiffusive Interaction.
Proceedings of the 2022 IEEE Sensors, Dallas, TX, USA, October 30 - Nov. 2, 2022, 2022
2021
Sensitivity, Noise and Resolution in a BEOL-Modified Foundry-Made ISFET with Miniaturized Reference Electrode for Wearable Point-of-Care Applications.
Sensors, 2021
2020
Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020
2019
Bayesian estimation of physical and geometrical parameters for nanocapacitor array biosensors.
J. Comput. Phys., 2019
Determination of Micro- and Nano-particle Properties by Multi-Frequency Bayesian Methods and Applications to Nanoelectrode Array Sensors.
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019
2018
A CMOS Pixelated Nanocapacitor Biosensor Platform for High-Frequency Impedance Spectroscopy and Imaging.
IEEE Trans. Biomed. Circuits Syst., 2018
2016
Performance study of strained III-V materials for ultra-thin body transistor applications.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique.
Int. J. Circuit Theory Appl., 2015
Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall.
Proceedings of the 1st IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2015
State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015
Proceedings of the 45th European Solid State Device Research Conference, 2015
2014
Numerical simulation of the position and orientation effects on the impedance response of nanoelectrode array biosensors to DNA and PNA strands.
Microelectron. J., 2014
Proceedings of the 37th International Convention on Information and Communication Technology, 2014
Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires.
Proceedings of the 44th European Solid State Device Research Conference, 2014
Proceedings of the 44th European Solid State Device Research Conference, 2014
2013
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013
Proceedings of the European Solid-State Device Research Conference, 2013
2012
A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2010
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators.
Int. J. Circuit Theory Appl., 2010
2009
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2005
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture.
IEEE J. Solid State Circuits, 2005
1990
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990