Luca Schiano

According to our database1, Luca Schiano authored at least 18 papers between 2002 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2006
Measuring the timing jitter of ATE in the frequency domain.
IEEE Trans. Instrum. Meas., 2006

Evaluating the Yield of Repairable SRAMs for ATE.
IEEE Trans. Instrum. Meas., 2006

HDLQ: A HDL environment for QCA design.
ACM J. Emerg. Technol. Comput. Syst., 2006

2005
Evaluation, analysis, and enhancement of error resilience for reliable compression of VLSI test data.
IEEE Trans. Instrum. Meas., 2005

Tile-based QCA design using majority-like logic primitives.
ACM J. Emerg. Technol. Comput. Syst., 2005

Evaluating the Data Integrity of Memory Systems by Configurable Markov Models.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Enhancing error resilience for reliable compression of VLSI test data.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories.
Proceedings of the 2005 Design, 2005

Evaluation of Error-Resilience for Reliable Compression of Test Data.
Proceedings of the 2005 Design, 2005

2004
Markov Models of Fault-Tolerant Memory Systems under SEU.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Error-Resilient Test Data Compression Using Tunstall Codes.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Scan Test of IP Cores in an ATE Environment.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003
Concurrent detection of power supply noise.
IEEE Trans. Reliab., 2003

Self-checking design, implementation, and measurement of a controller for track-side railway systems.
IEEE Trans. Instrum. Meas., 2003

A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

On the Test and Diagnosis of the Perfect Shuffle.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Self-Checking Scheme for the On-Line Testing of Power Supply Noise.
Proceedings of the 2002 Design, 2002


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