Luca Pezzarossa

Orcid: 0000-0002-0863-2526

According to our database1, Luca Pezzarossa authored at least 27 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Towards a tailored mixed-precision sub-8-bit quantization scheme for Gated Recurrent Units using Genetic Algorithms.
CoRR, 2024

Invited Paper: Worst-Case Execution Time Analysis of Lingua Franca Applications.
Proceedings of the 22nd International Workshop on Worst-Case Execution Time Analysis, 2024

Caching in a Mixed-Criticality 5G Radio Base Station.
Proceedings of the 3rd International Workshop on Resource AWareness of Systems and Society, Maribor, Slovenia, July 2nd, 2024

Towards Lingua Franca on the Patmos Processor.
Proceedings of the 27th IEEE International Symposium on Real-Time Distributed Computing, 2024

NeuralCasting: A Front-End Compilation Infrastructure for Neural Networks.
Proceedings of the 11th International Conference on Internet of Things: Systems, 2024

Hardware Generators with Chisel.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

2023
Chip Design and Verification in a Computer Engineering Education.
Computer, November, 2023

Transitioning to Chisel in University Education: Experiences and Lessons Learned.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

Intermittent Low-Power Wide Area Networks.
Proceedings of the 29th Annual International Conference on Mobile Computing and Networking, 2023

Dynamic nsNET2: Efficient Deep Noise Suppression with Early Exiting.
Proceedings of the 33rd IEEE International Workshop on Machine Learning for Signal Processing, 2023

AI-Based Detection of Droplets and Bubbles in Digital Microfluidic Biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

2020
A time-predictable open-source TTEthernet end-system.
J. Syst. Archit., 2020

2019
S4NOC: a minimalistic network-on-chip for real-time multicores.
Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

A Time-predictable TTEthenet Node.
Proceedings of the IEEE 22nd International Symposium on Real-Time Distributed Computing, 2019

A Minimal Network Interface for a Simple Network-on-Chip.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

2018
Reconfiguration of Computation and Communication Resources in Multi-Core Real-Time Embedded Systems.
PhD thesis, 2018

Using dynamic partial reconfiguration of FPGAs in real-Time systems.
Microprocess. Microsystems, 2018

A Multicore Processor for Time-Critical Applications.
IEEE Des. Test, 2018

2017
A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip.
J. Syst. Archit., 2017

Can real-time systems benefit from dynamic partial reconfiguration?
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

High-level synthesis for reduction of WCET in real-time systems.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Real-Time Audio Processing on the T-Crest Multicore Platform.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems.
Proceedings of the 20th IEEE International Symposium on Real-Time Distributed Computing, 2017

2016
Reconfiguration in FPGA-based multi-core platforms for hard real-time applications.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

An area-efficient TDM NoC supporting reconfiguration for mode changes.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

2015
Interfacing hardware accelerators to a time-division multiplexing network-on-chip.
Proceedings of the Nordic Circuits and Systems Conference, 2015


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