Luca Macchiarulo

According to our database, Luca Macchiarulo authored at least 40 papers between 1998 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

A jumper insertion algorithm under antenna ratio and timing constraints.

Xin Gao, Luca Macchiarulo

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

Digital Heart-Rate Variability Parameter Monitoring and Assessment ASIC.

Wansuree Massagram, Noah Hafner, Mingqi Chen, Luca Macchiarulo, Victor Lubecke, Olga Boric-Lubecke

IEEE Trans. Biomed. Circuits Syst., 2010

Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance.

Xin Gao, Luca Macchiarulo

Proceedings of the Design, Automation and Test in Europe, 2010

2009

A Case Study for NoC-Based Homogeneous MPSoC Architectures.

Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Macchiarulo, Maurizio Zamboni

IEEE Trans. Very Large Scale Integr. Syst., 2009

Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis.

Mario R. Casu, Luca Macchiarulo

Proceedings of the 4th International Workshop on the Application of Formal Methods for Globally Asynchronous and Locally Synchronous Design, 2009

2007

Adaptive Latency-Insensitive Protocols.

Mario R. Casu, Luca Macchiarulo

IEEE Des. Test Comput., 2007

2006

Floorplanning With Wire Pipelining in Adaptive Communication Channels.

Mario R. Casu, Luca Macchiarulo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Implementation analysis of NoC: a MPSoC trace-driven approach.

Sergio Tota, Mario R. Casu, Luca Macchiarulo

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Fully-Integrated Heart Rate Variability Monitoring System with an Efficient Memory.

Xiaoyue Wang, Mingqi Chen, Luca Macchiarulo, Olga Boric-Lubecke

Proceedings of the 28th International Conference of the IEEE Engineering in Medicine and Biology Society, 2006

Using Existing Digital Tools for Efficient Metabolic Pathway Simulations.

Luca Macchiarulo

Proceedings of the 28th International Conference of the IEEE Engineering in Medicine and Biology Society, 2006

2005

Throughput-driven floorplanning with wire pipelining.

Mario R. Casu, Luca Macchiarulo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Floorplan assisted data rate enhancement through wire pipelining: a real assessment.

Mario R. Casu, Luca Macchiarulo

Proceedings of the 2005 International Symposium on Physical Design, 2005

A New System Design Methodology for Wire Pipelined SoC.

Mario R. Casu, Luca Macchiarulo

Proceedings of the 2005 Design, 2005

2004

Pipelining Sequential Circuits with Wave Steering.

Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska

IEEE Trans. Computers, 2004

Floorplanning for throughput.

Mario R. Casu, Luca Macchiarulo

Proceedings of the 2004 International Symposium on Physical Design, 2004

On-Chip Transparent Wire Pipelining.

Mario R. Casu, Luca Macchiarulo

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A comparison between mask- and field-programmable routing structures on industrial FPGA architectures.

Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Issues in Implementing Latency Insensitive Protocols.

Mario R. Casu, Luca Macchiarulo

Proceedings of the 2004 Design, 2004

A new approach to latency insensitive design.

Mario R. Casu, Luca Macchiarulo

Proceedings of the 41th Design Automation Conference, 2004

2003

PITIA: an FPGA for throughput-intensive applications.

Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2003

New techniques for efficiently assessing reliability of SOCs.

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante

Microelectron. J., 2003

2002

Layout-driven memory synthesis for embedded systems-on-chip.

Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino

IEEE Trans. Very Large Scale Integr. Syst., 2002

An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits.

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante

J. Electron. Test., 2002

Enhanced clustered voltage scaling for low power.

Monica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis.

Pierluigi Civera, Luca Macchiarulo, Massimo Violante

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Wire Placement for Crosstalk Energy Minimization in Address Buses.

Luca Macchiarulo, Enrico Macii, Massimo Poncino

Proceedings of the 2002 Design, 2002

2001

Low-energy for deep-submicron address buses.

Luca Macchiarulo, Enrico Macii, Massimo Poncino

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Exploiting FPGA for Accelerating Fault Injection Experiments.

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits.

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante

Proceedings of the Field-Programmable Logic and Applications, 2001

Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits .

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

On-the-fly layout generation for PTL macrocells.

Luca Macchiarulo, Luca Benini, Enrico Macii

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip.

Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the 38th Design Automation Conference, 2001

FPGA-Based Fault Injection for Microprocessor Systems.

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'.

Elena Dubrova, Luca Macchiarulo

IEEE Trans. Computers, 2000

A novel high throughput reconfigurable FPGA architecture.

Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Wave Steered FSMs.

Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska

Proceedings of the 2000 Design, 2000

Wave-steering one-hot encoded FSMs.

Luca Macchiarulo, Malgorzata Marek-Sadowska

Proceedings of the 37th Conference on Design Automation, 2000

1999

Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases.

Luca Macchiarulo, Pierluigi Civera

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998

Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis.

Luca Macchiarulo, Pierluigi Civera

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Artificial Neural Networks for Motion Emulation in Virtual Environments.

Y. Bellan, Mario Costa, Giancarlo Ferrigno, Fabrizio Lombardi, Luca Macchiarulo, Alfonso Montuori, Eros Pasero, Camilla Rigotti

Proceedings of the Modelling and Motion Capture Techniques for Virtual Environments, 1998