Luca G. Amarù

Affiliations:
  • Synopsys Inc, Mountain View, CA, USA


According to our database1, Luca G. Amarù authored at least 71 papers between 2011 and 2024.

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Bibliography

2024
Scalable Sequential Optimization Under Observability Don't Cares.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2022
Majority-based Design Flow for AQFP Superconducting Family.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Improving LUT-based optimization for ASICs.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Deep Integration of Circuit Simulator and SAT Solver.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

LUT-Based Optimization For ASIC Design Flow.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks.
IACR Cryptol. ePrint Arch., 2020

Extending Boolean Methods for Scalable Logic Synthesis.
IEEE Access, 2020

A Scalable Mixed Synthesis Framework for Heterogeneous Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

SAT-Sweeping Enhanced for Logic Synthesis.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Mapping Monotone Boolean Functions into Majority.
IEEE Trans. Computers, 2019

Logic Synthesis for Established and Emerging Computing.
Proc. IEEE, 2019

Logic Optimization of Majority-Inverter Graphs.
Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

Scalable Boolean Methods in a Modern Synthesis Flow.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Scalable Generic Logic Synthesis: One Approach to Rule Them All.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Size Optimization of MIGs with an Application to QCA and STMG Technologies.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Integrated ESOP Refactoring for Industrial Designs.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Majority logic synthesis.
Proceedings of the International Conference on Computer-Aided Design, 2018

Practical exact synthesis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Technology-aware logic synthesis for ReRAM based in-memory computing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improvements to boolean resynthesis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Canonical computation without canonical representation.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Exact Synthesis of Majority-Inverter Graphs and Its Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Enabling exact delay synthesis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Wave pipelining for majority-based beyond-CMOS technologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Logic optimization and synthesis: Trends and directions in industry.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A novel basis for logic rewriting.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Multi-level logic benchmarks: An exactness study.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Majority-Inverter Graph: A New Paradigm for Logic Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Sound and Complete Axiomatization of Majority-n Logic.
IEEE Trans. Computers, 2016

Inversion optimization in Majority-Inverter Graphs.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications.
Proceedings of the 17th Latin-American Test Symposium, 2016

Notes on Majority Boolean Algebra.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Digital, analog and RF design opportunities of three-independent-gate transistors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Optimizing Majority-Inverter Graphs with functional hashing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

The Programmable Logic-in-Memory (PLiM) computer.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

An MIG-based compiler for programmable logic-in-memory architectures.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Majority-based synthesis for nanotechnologies.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
New Data Structures and Algorithms for Logic Synthesis and Verification.
PhD thesis, 2015

New Logic Synthesis as Nanotechnology Enabler.
Proc. IEEE, 2015

NEM relay design with biconditional binary decision diagrams.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A fast pruning technique for low-power inexact Circuit design.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Exploiting Circuit Duality to Speed up SAT.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Multiple Independent Gate FETs: How many gates do we need?
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

System-level assessment and area evaluation of Spin Wave logic circuits.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A new basic logic structure for data-path computation (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Majority Logic Synthesis for Spin Wave Technology.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Advanced system on a chip design based on controllable-polarity FETs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An efficient manipulation package for Biconditional Binary Decision Diagrams.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Data compression via logic synthesis.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.
Proceedings of the Design, Automation and Test in Europe, 2013

Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

Towards structured ASICs using polarity-tunable Si nanowire transistors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
High Speed Architectures for Finding the First two Maximum/Minimum Values.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2011
Nanofabric power analysis: Biosequence alignment case study.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011


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