Luca Colagrande
Orcid: 0000-0002-7986-1975
According to our database1,
Luca Colagrande
authored at least 5 papers
between 2024 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
2024
2025
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Bibliography
2025
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET.
CoRR, January, 2025
2024
Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform.
CoRR, 2024
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024