Luca Breveglieri

J. Comput. Lang., January, 2023

2021

Fast GLR parsers for extended BNF grammars and transition networks.

[BibT_eX]

[DOI]

J. Comput. Lang., 2021

A deterministic parsing algorithm for ambiguous regular expressions.

[BibT_eX]

[DOI]

Acta Informatica, 2021

Exploring Cortex-M Microarchitectural Side Channel Information Leakage.

[BibT_eX]

[DOI]

IEEE Access, 2021

2020

A Generalized LR(1) Parser or Extended Context-Free Grammars.

[BibT_eX]

[DOI]

Proceedings of the 21st Italian Conference on Theoretical Computer Science, 2020

2019

Formal Languages and Compilation, Third Edition

[BibT_eX]

[DOI]

Texts in Computer Science, Springer, ISBN: 978-3-030-04878-5, 2019

A Benchmark Production Tool for Regular Expressions.

[BibT_eX]

[DOI]

Proceedings of the Implementation and Application of Automata, 2019

A secure and authenticated host-to-memory communication interface.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018

Fast deterministic parsers for transition networks.

[BibT_eX]

[DOI]

Acta Informatica, 2018

Software-only Reverse Engineering of Physical DRAM Mappings for Rowhammer Attacks.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

2016

A Fault-Based Secret Key Retrieval Method for ECDSA: Analysis and Countermeasure.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2016

2015

BSP: A Parsing Tool for Ambiguous Regular Expressions.

[BibT_eX]

[DOI]

Proceedings of the Implementation and Application of Automata, 2015

From Ambiguous Regular Expressions to Deterministic Parsing Automata.

[BibT_eX]

[DOI]

Proceedings of the Implementation and Application of Automata, 2015

2014

Shift-Reduce Parsers for Transition Networks.

[BibT_eX]

[DOI]

Proceedings of the Language and Automata Theory and Applications, 2014

Complexity of Extended vs. Classic LR Parsers.

[BibT_eX]

[DOI]

Proceedings of the Descriptional Complexity of Formal Systems, 2014

2013

Formal Languages and Compilation, Second Edition.

[BibT_eX]

[DOI]

Texts in Computer Science, Springer, ISBN: 978-1-4471-5514-0, 2013

A fault induction technique based on voltage underfeeding with application to attacks against AES and RSA.

[BibT_eX]

[DOI]

J. Syst. Softw., 2013

Parsing methods streamlined.

[BibT_eX]

[DOI]

CoRR, 2013

2012

Interaction Between Fault Attack Countermeasures and the Resistance Against Power Analysis Attacks.

[BibT_eX]

[DOI]

Proceedings of the Fault Analysis in Cryptography, 2012

Injection Technologies for Fault Attacks on Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the Fault Analysis in Cryptography, 2012

Fault Injection Attacks on Cryptographic Devices: Theory, Practice, and Countermeasures.

[BibT_eX]

[DOI]

Proc. IEEE, 2012

2011

Fault attack to the elliptic curve digital signature algorithm with multiple bit faults.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Security of Information and Networks, 2011

2010

Efficient recognition of trace languages defined by repeat-until loops.

[BibT_eX]

[DOI]

Massimiliano Goldwurm

Inf. Comput., 2010

Low Voltage Fault Attacks to AES and RSA on General Purpose Processors.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2010

Low Voltage Fault Attacks to AES.

[BibT_eX]

[DOI]

Proceedings of the HOST 2010, 2010

Countermeasures against fault attacks on software implemented AES: effectiveness and cost.

[BibT_eX]

[DOI]

Proceedings of the 5th Workshop on Embedded Systems Security, 2010

Fault attack on AES with single-bit induced faults.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Information Assurance and Security, 2010

2009

Alphabetical Satisfiability Problem for Trace Equations.

[BibT_eX]

[DOI]

Acta Cybern., 2009

Practical Power Analysis Attacks to RSA on a Large IP Portfolio SoC.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

2008

A pairing SW implementation for Smart-Cards.

[BibT_eX]

[DOI]

J. Syst. Softw., 2008

Parallel Hardware Architectures for the Cryptographic Tate Pairing.

[BibT_eX]

[DOI]

Int. J. Netw. Secur., 2008

A 640 Mbit/S 32-Bit Pipelined Implementation of the AES Algorithm.

[BibT_eX]

Proceedings of the SECRYPT 2008, 2008

A FPGA Coprocessor for the Cryptographic Tate Pairing over Fp.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Information Technology: New Generations (ITNG 2008), 2008

Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

NP-completeness of the alphabetical satisfiability problem for trace equations.

[BibT_eX]

Proceedings of the Automata and Formal Languages, 12th International Conference, 2008

2007

An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

Programming Highly Parallel Reconfigurable Architectures for Symmetric and Asymmetric Cryptographic Applications.

[BibT_eX]

[DOI]

J. Comput., 2007

Programming Highly Parallel Reconfigurable Architectures for Public-Key Cryptographic Applications.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

Countermeasures against Branch Target Buffer Attacks.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007

Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006

Guest Editors' Introduction: Special Section on Fault Diagnosis and Tolerance in Cryptography.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Power Aware Design of an Elliptic Curve Coprocessor for 8 bit Platforms.

[BibT_eX]

[DOI]

Guido Bertoni

Matteo Venturi

Proceedings of the 4th IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2006 Workshops), 2006

ECC Hardware Coprocessors for 8-bit Systems and Power Consumption Considerations.

[BibT_eX]

[DOI]

Guido Bertoni

Matteo Venturi

Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

A Note on Error Detection in an RSA Architecture by Means of Residue Codes.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Performance of HECC Coprocessors Using Inversion-Free Formulae.

[BibT_eX]

[DOI]

Proceedings of the Computational Science and Its Applications, 2006

Incorporating Error Detection in an RSA Architecture.

[BibT_eX]

[DOI]

Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

A Fault Attack Against the FOX Cipher Family.

[BibT_eX]

[DOI]

Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

Software implementation of Tate pairing over GF(2<sup>m</sup>).

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Speeding Up AES By Extending a 32 bit Processor Instruction Set.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005

A Parallelized Design for an Elliptic Curve Cryptosystem Coprocessor.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

AES Power Attack Based on Induced Cache Miss and Countermeasure.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

On-Line Testing for Secure Implementations: Design and Validation.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A Complete Formulation of Generalized Affine Equivalence.

[BibT_eX]

[DOI]

Proceedings of the Theoretical Computer Science, 9th Italian Conference, 2005

Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2004

Efficient AES implementations for ARM based platforms.

[BibT_eX]

[DOI]

Kubilay Atasu

Marco Macchetti

Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Workshop on Fault Diagnosis and Tolerance in Cryptography.

[BibT_eX]

Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004

An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

On the Generalized Linear Equivalence of Functions Over Finite Fields.

[BibT_eX]

[DOI]

Marco Macchetti

Proceedings of the Advances in Cryptology, 2004

Detecting Faults in Four Symmetric Key Block Ciphers.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003

Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

About the performances of the Advanced Encryption Standard in embedded systems with cache memory.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002

Digital Median Filters.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2002

A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Efficient Software Implementation of AES on 32-Bit Platforms.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems, 2002

On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001

Efficient finite field digital-serial multiplier architecture for cryptography applications.

[BibT_eX]

[DOI]

Guido Bertoni

Pasqualina Fragneto

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Dedicated Circuits for the Generation of Windows in Image Processing Architectures.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2000

1999

Modeling Operating Systems Schedulers with Multi-Stack-Queue Grammars.

[BibT_eX]

[DOI]

Proceedings of the Fundamentals of Computation Theory, 12th International Symposium, 1999

1998

A VLSI inner product macrocell.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

1997

Fair Expressions and Regular Languages over Lists.

[BibT_eX]

[DOI]

RAIRO Theor. Informatics Appl., 1997

Fast Arithmetic and Fault Tolerance in the FERMI System.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996

Multi-Push-Down Languages and Grammars.

[BibT_eX]

[DOI]

Claudio Citrini

Int. J. Found. Comput. Sci., 1996

Balancing of Fault Tolerance in the New Version of the FERMI Channel Chip: a Functional Evaluation.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

Deterministic Parsing for Augmented Context-free Grammars.

[BibT_eX]

[DOI]

Proceedings of the Mathematical Foundations of Computer Science 1995, 1995

A model for the evaluation of fault tolerance in the FERMI system.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

Column Compression Pipelined Multipliers.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994

A fast pipelined FFT unit.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Application Specific Array Processors, 1994

1993

Modular design methodologies for image processing architectures.

[BibT_eX]

[DOI]

Alberto Avai

IEEE Trans. Very Large Scale Integr. Syst., 1993

Modular Design Methodologies for Image Processing Architectures.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on VLSI Design, 1993

Fair First Languages and Parallel Programme Schemes.

[BibT_eX]

Claudio Citrini

Proceedings of the Developments in Language Theory, 1993

System Level Policies for Fault Tolerance Issues in the FERMI Project.

[BibT_eX]

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992

Window-based dedicated parallel architectures for image processing.

[BibT_eX]

[DOI]

Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992

Real-Time Scheduling by Queue Automata.

[BibT_eX]

[DOI]

Proceedings of the Formal Techniques in Real-Time and Fault-Tolerant Systems, 1992

1991

Deterministic Dequeue Automata and LL(1) Parsing of Breadth-Depth Grammars.

[BibT_eX]

[DOI]

Claudio Citrini

Proceedings of the Fundamentals of Computation Theory, 8th International Symposium, 1991

1990

Testing of serial input convolvers.

[BibT_eX]

[DOI]

Donatella Sciuto

Microprocessing and Microprogramming, 1990

1988

Design and implementation of a VLSI serial multiplier for fixed point numbers with self-checking capability.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1988

A serial-input serial-output bit-sliced convolver.

[BibT_eX]

[DOI]