Luca Bertaccini
According to our database1,
Luca Bertaccini
authored at least 12 papers
between 2021 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform.
CoRR, 2024
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
RedMule: A mixed-precision matrix-matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration.
Future Gener. Comput. Syst., December, 2023
Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays.
CoRR, 2023
ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I<sup>2</sup>S DSP for Flexible Data Acquisition from Microphone Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores.
Proceedings of the 29th IEEE Symposium on Computer Arithmetic, 2022
2021
RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range.
Proceedings of the 47th ESSCIRC 2021, 2021
To Buffer, or Not to Buffer? A Case Study on FFT Accelerators for Ultra-Low-Power Multicore Clusters.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021