Luca Avallone

Orcid: 0000-0002-2243-5588

According to our database1, Luca Avallone authored at least 9 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.
IEEE J. Solid State Circuits, March, 2023

2022
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping.
IEEE J. Solid State Circuits, 2022

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time.
IEEE J. Solid State Circuits, 2022

A 68.6fs<sub>rms</sub>-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
Jitter Minimization in Digital PLLs with Mid-Rise TDCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020


  Loading...