Luc Rijnders

According to our database, Luc Rijnders authored at least 11 papers between 1988 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Towards high performance sub-10nm finW bulk FinFET technology.

Thomas Chiarella, Stefan Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, An De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2006

System Level Architecture Exploration for Reconfigurable Systems On Chip.

Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2003

Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java.

Richard Stahl, Robert Pasko, Luc Rijnders, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, Francky Catthoor

Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

2001

High-performance flexible all-digital quadrature up and down converter chip.

Robert Pasko, Luc Rijnders, Patrick R. Schaumont, Serge A. Vernalde, Daniela Duracková

IEEE J. Solid State Circuits, 2001

2000

A Hardware Virtual Machine for the Networked Reconfiguration.

Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man

Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

1999

A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement.

Radim Cmar, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Ivo Bolsens

Proceedings of the 1999 Design, 1999

1998

A Programming Environment for the Design of Complex High Speed ASICs.

Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens

Proceedings of the 35th Conference on Design Automation, 1998

1997

Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications.

Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens

Proceedings of the European Design and Test Conference, 1997

1995

Timing optimization by bit-level arithmetic transformations.

Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De Man

Proceedings of the Proceedings EURO-DAC'95, 1995

1989

REDUSA: module generation by automatic elimination of superfluous blocks in regular structures.

I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988

Design of a process-tolerant cell library for regular structures using symbolic layout and hierarchical compaction.

Luc Rijnders, Paul Six, Hugo J. De Man

IEEE J. Solid State Circuits, June, 1988