Lu Peng

Proceedings of the IEEE International Conference on Blockchain, 2023

2022

Protecting Synchronization Mechanisms of Parallel Big Data Kernels via Logging.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Ensemble of fast learning stochastic gradient boosting.

[BibT_eX]

[DOI]

Qingzhao Yu

Commun. Stat. Simul. Comput., 2022

High performance GPU concurrent B+tree.

[BibT_eX]

[DOI]

Proceedings of the PPoPP '22: 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Seoul, Republic of Korea, April 2, 2022

Cascade Variational Auto-Encoder for Hierarchical Disentanglement.

[BibT_eX]

[DOI]

Proceedings of the 31st ACM International Conference on Information & Knowledge Management, 2022

GeauxTrace: A Scalable Privacy-Protecting Contact Tracing App Design Using Blockchain.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Big Data Computing, 2022

2021

iChain: Peer-To-Peer Machine Learning Powered by Blockchain Technology.

[BibT_eX]

[DOI]

Frontiers Blockchain, 2021

Evaluation of Algorithms for Randomizing Key Item Locations in Game Worlds.

[BibT_eX]

[DOI]

IEEE Access, 2021

Precise Weather Parameter Predictions for Target Regions via Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Machine Learning and Knowledge Discovery in Databases. Applied Data Science Track, 2021

GPU-Assisted Memory Expansion.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021

BifurKTM: Approximately Consistent Distributed Transactional Memory for GPUs.

[BibT_eX]

[DOI]

Proceedings of the 12th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and 10th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2021

2020

A High Throughput B+tree for SIMD Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2020

Architectural Support for NVRAM Persistence in GPUs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2020

Computer comparisons in the presence of performance variation.

[BibT_eX]

[DOI]

Frontiers Comput. Sci., 2020

Robust Cache-Aware Quantum Processor Layout.

[BibT_eX]

[DOI]

Travis LeCompte

Fang Qi

Proceedings of the International Symposium on Reliable Distributed Systems, 2020

ATT: A Fault-Tolerant ReRAM Accelerator for Attention-based Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

BPU: A Blockchain Processing Unit for Accelerated Smart Contract Execution.

[BibT_eX]

[DOI]

Tao Lu

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Hierarchical Hybrid Memory Management in OS for Tiered Memory Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2019

Long Short-Term Memory Network Design for Analog Computing.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2019

Harmonia: a high throughput B+tree for GPUs.

[BibT_eX]

[DOI]

Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2019

CUDA-DTM: Distributed Transactional Memory for GPU Clusters.

[BibT_eX]

[DOI]

Christopher J. Michael

Proceedings of the Networked Systems - 7th International Conference, 2019

Exploiting Model-Level Parallelism in Recurrent Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Hardware Accelerator for Adversarial Attacks on Deep Learning Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

Efficient GPU NVRAM Persistence with Helper Warps.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Fooling AI with AI: An Accelerator for Adversarial Attacks on Deep Learning Visual Classification.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

Thinking about A New Mechanism for Huge Page Management.

[BibT_eX]

[DOI]

Proceedings of the 10th ACM SIGOPS Asia-Pacific Workshop on Systems, 2019

2018

qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and Remote Accesses.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Multiple Input Floating Gate Based Arithmetic Logic Unit with a Feedback Loop for Digital Calibration.

[BibT_eX]

[DOI]

J. Low Power Electron., 2018

Calibration method to reduce the error in logarithmic conversion with its circuit implementation.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2018

2017

Using Switchable Pins to Increase Off-Chip Bandwidth in Chip-Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2017

Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

Soft error resilience of Big Data kernels through algorithmic approaches.

[BibT_eX]

[DOI]

J. Supercomput., 2017

QoS Management on Heterogeneous Architecture for Multiprogrammed, Parallel, and Domain-Specific Applications.

[BibT_eX]

[DOI]

IEEE Syst. J., 2017

Emerging technology enabled energy-efficient GPGPUs register file.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

A novel switchable pin method for regulating power in chip-multiprocessor.

[BibT_eX]

[DOI]

Integr., 2017

Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Accelerating GPU Hardware Transactional Memory with Snapshot Isolation.

[BibT_eX]

[DOI]

Sui Chen

Samuel Irving

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Carpool: a bufferless on-chip network supporting adaptive multicast and hotspot alleviation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Supercomputing, 2017

2016

Performance Analysis of Multimedia Retrieval Workloads Running on Multicores.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

Soft error resilience in Big Data kernels through modular analysis.

[BibT_eX]

[DOI]

J. Supercomput., 2016

Operational Cost Optimization for Cloud Computing Data Centers Using Renewable Energy.

[BibT_eX]

[DOI]

Shaoming Chen

Samuel Irving

IEEE Syst. J., 2016

Design space exploration for device and architectural heterogeneity in chip-multiprocessors.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Parallelizing image feature extraction algorithms on multi-core platforms.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2016

A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Efficient GPU hardware transactional memory through early conflict resolution.

[BibT_eX]

[DOI]

Sui Chen

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015

A framework for evaluating comprehensive fault resilience mechanisms in numerical programs.

[BibT_eX]

[DOI]

J. Supercomput., 2015

Powering Up Dark Silicon: Mitigating the Limitation of Power Delivery via Dynamic Pin Switching.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2015

Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneity.

[BibT_eX]

[DOI]

Integr., 2015

Precise computer comparisons via statistical resampling methods.

[BibT_eX]

[DOI]

Shaoming Chen

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Circuit Implementation of Switchable Pins in Chip Multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014

Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Design configuration selection for hard-error reliable processors via statistical rules.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Increasing off-chip bandwidth in multi-core processors with switchable pins.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

QoS management on heterogeneous architecture for parallel applications.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Predicting Architectural Vulnerability on Multithreaded Processors under Resource Contention and Sharing.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2013

Effective thermal control techniques for liquid-cooled 3D multi-core processors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Lighting the dark silicon by exploiting heterogeneity on future processors.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Optimization of Electricity and Server Maintenance Costs in Hybrid Cooling Data Centers.

[BibT_eX]

[DOI]

Shaoming Chen

Yue Hu

Proceedings of the 2013 IEEE Sixth International Conference on Cloud Computing, Santa Clara, CA, USA, June 28, 2013

2012

Model guided adaptive design and analysis in computer experiment.

[BibT_eX]

[DOI]

Stat. Anal. Data Min., 2012

Optimal microarchitectural design configuration selection for processor hard-error reliability.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

Efficient Prefetching with Hybrid Schemes and Use of Program Feedback to Adjust Prefetcher Aggressiveness.

[BibT_eX]

[DOI]

Santhosh Verma

David M. Koppelman

J. Instr. Level Parallelism, 2011

Enhancements for Accurate and Timely Streaming Prefetcher.

[BibT_eX]

[DOI]

J. Instr. Level Parallelism, 2011

Performance and Power Analysis of ATI GPU: A Statistical Approach.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

Universal rules guided design parameter selection for soft error resilient processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Architecture comparisons between Nvidia and ATI GPUs: Computation parallelism and data communications.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

Two-level soft error vulnerability prediction on SMT/CMP architectures.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

Tree structured analysis on GPU power study.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Statistical GPU power analysis using tree-based methods.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

2010

Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

A Host-Based Intrusion Detection System Using Architectural Features to Improve Sophisticated Denial-of-Service Attack Detections.

[BibT_eX]

[DOI]

Int. J. Inf. Secur. Priv., 2010

Expediating IP lookups with reduced power via TBM and SST supernode caching.

[BibT_eX]

[DOI]

Comput. Commun., 2010

Weak execution ordering - exploiting iterative methods on many-core GPUs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

2009

Accurate and efficient processor performance prediction via regression tree based modeling.

[BibT_eX]

[DOI]

Balachandran Ramadass

J. Syst. Archit., 2009

Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

A case study: Using architectural features to improve sophisticated denial-of-service attack detections.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE Symposium on Computational Intelligence in Cyber Security, 2009

2008

Memory hierarchy performance measurement of commercial dual-core desktop processors.

[BibT_eX]

[DOI]

J. Syst. Archit., 2008

SecCMP: Enhancing Critical Secrets Protection in Chip-Multiprocessors.

[BibT_eX]

[DOI]

Li Yang

Balachandran Ramadass

Int. J. Inf. Secur. Priv., 2008

Efficient mart-aided modeling for microarchitecture design space exploration and performance prediction.

[BibT_eX]

[DOI]

Balachandran Ramadass

Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2008

2007

Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Performance Computing and Communications Conference, 2007

Power Efficient IP Lookup with Supernode Caching.

[BibT_eX]

[DOI]

Wencheng Lu

Proceedings of the Global Communications Conference, 2007

2006

Coterminous locality and coterminous group data prefetching on chip-multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

SecCMP: a secure chip-multiprocessor architecture.

[BibT_eX]

[DOI]

Li Yang

Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, 2006

2004

A New Address-Free Memory Hierarchy Layer for Zero-Cycle Load.

[BibT_eX]

[DOI]

Jih-Kwon Peir

Konrad Lai

J. Instr. Level Parallelism, 2004

Signature Buffer: Bridging Performance Gap between Registers and Caches.

[BibT_eX]

[DOI]