Lu Lu

Orcid: 0000-0001-6745-622X

Affiliations:
  • Nanyang Technological University, School of Electrical and Electronic Engineering, Singapore


According to our database1, Lu Lu authored at least 21 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

2023
A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Computing-In-Memory for Advanced Edge AI Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
A High Reliable SRAM-Based PUF With Enhanced Challenge-Response Space.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Temperature Compensation on SRAM-Based Computation in Memory Array.
Proceedings of the 19th International SoC Design Conference, 2022

A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications.
IEEE Open J. Circuits Syst., 2021

A Configurable Randomness Enhanced RRAM PUF with Biased Current Sensing Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Programmable 6T SRAM-Based PUF with Dynamic Stability Data Masking.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019
Improving uniformity and reliability of SRAM PUFs utilizing device aging phenomenon for unique identifier generation.
Microelectron. J., 2019

A Sequence-Dependent Configurable PUF Based on 6T SRAM for Enhanced Challenge Response Space.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
An Ultra-low Power 8T SRAM with Vertical Read Word Line and Data Aware Write Assist.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018


  Loading...