Lovic Gauthier
Orcid: 0000-0001-6914-115X
According to our database1,
Lovic Gauthier
authored at least 24 papers
between 2000 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
2000
2005
2010
2015
2020
0
1
2
3
4
5
6
1
1
1
1
1
2
2
1
2
1
2
1
2
3
3
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
HDLRuby: A Ruby Extension for Hardware Description and Its Translation to Synthesizable Verilog HDL.
ACM Trans. Embed. Comput. Syst., September, 2024
2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
2013
Hybrid compile and run-time memory management for a 3D-stacked reconfigurable accelerator.
Proceedings of the International Conference on Compilers, 2013
2012
J. Electr. Comput. Eng., 2012
2011
Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
An integrated optimization framework for reducing the energy consumption of embedded real-time applications.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems.
Proceedings of the 2010 International Conference on Compilers, 2010
2009
Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories.
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009
2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
2004
Object-based hardware/software component interconnection model for interface design in system-on-a-chip circuits.
J. Syst. Softw., 2004
2002
Tech. Sci. Informatiques, 2002
IEEE Des. Test Comput., 2002
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design.
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
Automatic generation and targeting of application-specificoperating systems and embedded systems software.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Des. Test Comput., 2001
Colif: a Multilevel Design Representation for Application-Specific Multiprocessor System-on-Chip Design.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001
Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
Automatic generation and targeting of application specific operating systems and embedded systems software.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Cycle-True Simulation of the ST10 Microcontroller Including the Core and the Peripherals.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000
Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000
Proceedings of the 2000 Design, 2000