Louis Y.-Z. Lin
Orcid: 0000-0002-4563-3843
According to our database1,
Louis Y.-Z. Lin
authored at least 9 papers
between 2013 and 2019.
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Bibliography
2019
P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings.
IEEE Access, 2019
2018
Unleashing Parallelism With Minimal Test Inflation in Multi-Threaded Test Pattern Generation.
IEEE Access, 2018
2017
Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax?
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
Speed binning with high-quality structural patterns from functional timing analysis (FTA).
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Proceedings of the 43rd International Conference on Parallel Processing, 2014
Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013