Lorenzo Scaletti

Orcid: 0000-0002-3979-6320

According to our database1, Lorenzo Scaletti authored at least 6 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2023
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2022
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022


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