Lorenzo Scaletti
Orcid: 0000-0002-3979-6320
According to our database1,
Lorenzo Scaletti
authored at least 7 papers
between 2022 and 2025.
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2025
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk.
IEEE J. Solid State Circuits, February, 2025
2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
2022
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022