Lorenzo Chelini

Orcid: 0000-0001-8539-2397

Affiliations:
  • Eindhoven University of Technology, The Netherlands


According to our database1, Lorenzo Chelini authored at least 16 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

On csauthors.net:

Bibliography

2024
Towards a high-performance AI compiler with upstream MLIR.
CoRR, 2024

SEER: Super-Optimization Explorer for High-Level Synthesis using E-graph Rewriting.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR.
CoRR, 2023

CINM (Cinnamon): A Compilation Infrastructure for Heterogeneous Compute In-Memory and Compute Near-Memory Paradigms.
CoRR, 2023

2022
OCC: An Automated End-to-End Machine Learning Optimizing Compiler for Computing-In-Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

MOM: Matrix Operations in MLIR.
CoRR, 2022

2021
LoopOpt: Declarative Transformations Made Easy.
Proceedings of the SCOPES '21: 24th International Workshop on Software and Compilers for Embedded Systems, Eindhoven, The Netherlands, November 1, 2021

Progressive Raising in Multi-level IR.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021

Polygeist: Raising C to Polyhedral MLIR.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020
Declarative Loop Tactics for Domain-specific Optimization.
ACM Trans. Archit. Code Optim., 2020

PET-to-MLIR: A polyhedral front-end for MLIR.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

TDO-CIM: Transparent Detection and Offloading for Computation In-memory.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Automatic Generation of Multi-Objective Polyhedral Compiler Transformations.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
Near-memory computing: Past, present, and future.
Microprocess. Microsystems, 2019

Coherently Attached Programmable Near-Memory Acceleration Platform and its application to Stencil Processing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A Review of Near-Memory Computing Architectures: Opportunities and Challenges.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018


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