Longmei Nan

According to our database1, Longmei Nan authored at least 17 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
A Domain-Specific DMA Structure for Per-channel Processing-based CNN Accelerator.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
An energy-efficient reconfigurable asymmetric modular cryptographic operation unit for RSA and ECC.
Frontiers Inf. Technol. Electron. Eng., 2022

A side-channel-attack countermeasure for elliptic curve point multiplication based on dynamic power compensation.
IEICE Electron. Express, 2022

High Efficient Architecture of Polynomial Multiplier with Variable Parameter Based on 2KNTT.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
A high-efficient and low-cost secure AMBA framework utilizing configurable data encryption modeling against probe attacks.
IEICE Electron. Express, 2021

An Efficient Module Arithmetic Logic Unit in Dual Field for Internet of Things Applications.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

Effective Register Allocation for Configurable VLIW Crypto-Processor.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping.
IEEE Trans. Very Large Scale Integr. Syst., 2020

65 nm sub-threshold logic standard cell library using quasi-Schmitt-trigger design scheme and inverse narrow width effect aware sizing.
IET Circuits Devices Syst., 2020

2019
Transparent Buffer Management: An Intra-cluster Task Scheduling Method Based on Dynamic Virtual Channel.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications.
IEICE Electron. Express, 2018

2017
RC6 architecture-adaptive implementation for coarse-grained reconfiguration array.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

An area-efficient interconnection network for coarse-grain reconfigurable cryptographic array.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2013
Design and Implementation of Configurable LFSR Instructions Targeted at Stream Cipher Processing.
J. Circuits Syst. Comput., 2013

The Design of Video Accelerator Bus Wrapper.
Proceedings of the Computer Engineering and Technology - 17th CCF Conference, 2013

2008
Research and Implementation of a High-Speed Reconfigurable A5 Algorithm.
Proceedings of the PACIIA 2008, 2008


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