Lomash Chandra Acharya
Orcid: 0000-0002-6444-8483
According to our database1,
Lomash Chandra Acharya
authored at least 9 papers
between 2021 and 2023.
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Bibliography
2023
Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations.
Microelectron. J., December, 2023
Generalized Edge Propagation and Multi-Band Frequency Switching Mechanism for MSSROs.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure.
Proceedings of the 19th International Conference on Synthesis, 2023
ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021