Loïs Guiller

According to our database, Loïs Guiller authored at least 15 papers between 1999 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

A Gated Clock Scheme for Low Power Testing of Logic Cores.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

J. Electron. Test., 2006

2004

Power-Driven Routing-Constrained Scan Chain Design.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

J. Electron. Test., 2004

Design of Routing-Constrained Low Power Scan Chains.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Integrating DFT in the Physical Synthesis Flow.

Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A Gated Clock Scheme for Low Power Scan-Based BIST.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Low Power BIST by Filtering Non-Detecting Vectors.

Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos

J. Electron. Test., 2000

Low power BIST design by hypergraph partitioning: methodology and architectures.

Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

An adjacency-based test pattern generator for low power BIST design.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

A Test Vector Inhibiting Technique for Low Energy BIST Design.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999