Loganath Ramachandran

According to our database1, Loganath Ramachandran authored at least 10 papers between 1991 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2003
Specification and Design of Multi-Million Gate SOCs.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

1996
System design methodologies: aiming at the 100 h design cycle.
IEEE Trans. Very Large Scale Integr. Syst., 1996

1994
Introduction to High-Level Synthesis.
IEEE Des. Test Comput., 1994

100-hour design cycle: a test case.
Proceedings of the Proceedings EURO-DAC'94, 1994

An Algorithm for Array Variable Clustering.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Synthesis of functions and procedures in behavioral VHDL.
Proceedings of the European Design Automation Conference 1993, 1993

Architectural tradeoffs in synthesis of pipelined controls.
Proceedings of the European Design Automation Conference 1993, 1993

High-Level Transformations for Minimizing Syntactic Variances.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Semantics and synthesis of signals in behavioral VHDL.
Proceedings of the conference on European design automation, 1992

1991
An Algorithm for Component Selection in Performance Optimized Scheduling.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991


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