Logan Rakai
Orcid: 0000-0002-4634-2183Affiliations:
- University of Calgary, Canada
According to our database1,
Logan Rakai
authored at least 33 papers
between 2006 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
Proceedings of the 2022 IEEE/IFIP Network Operations and Management Symposium, 2022
2021
IEEE Trans. Cloud Comput., 2021
2020
Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2018
J. Comput. Appl. Math., 2018
A machine learning framework to identify detailed routing short violations from a placed netlist.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
IEEE Trans. Netw. Serv. Manag., 2017
A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock Trees.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
A Parallel Method for the Computation of Matrix Exponential Based on Truncated Neumann Series.
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017
2016
Big Data Analytics for Modelling the Impact of Wind Power Generation on Competitive Electricity Market Prices.
Proceedings of the 49th Hawaii International Conference on System Sciences, 2016
2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 14th IEEE International Conference on Machine Learning and Applications, 2015
Proceedings of the 2015 IEEE Global Communications Conference, 2015
Proceedings of the Computational Intelligence in Digital and Network Designs and Applications, 2015
2014
Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Proceedings of the 47th Hawaii International Conference on System Sciences, 2014
2013
A new a priori net length estimation technique for integrated circuits using radial basis functions.
Comput. Electr. Eng., 2013
Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes.
Proceedings of the International Symposium on Physical Design, 2013
A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
PhD thesis, 2012
Appl. Math. Comput., 2012
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012
2011
A pre-placement individual net length estimation model and an application for modern circuits.
Integr., 2011
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011
2009
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006