Lluís Vilanova

Orcid: 0000-0002-1452-840X

Affiliations:
  • Imperial College London, UK


According to our database1, Lluís Vilanova authored at least 23 papers between 2009 and 2023.

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Bibliography

2023
QuanShield: Protecting against Side-Channels Attacks using Self-Destructing Enclaves.
CoRR, 2023

Faabric: Fine-Grained Distribution of Scientific Workloads in the Cloud.
CoRR, 2023

Translation Pass-Through for Near-Native Paging Performance in VMs.
Proceedings of the 2023 USENIX Annual Technical Conference, 2023

ORC: Increasing Cloud Memory Density via Object Reuse with Capabilities.
Proceedings of the 17th USENIX Symposium on Operating Systems Design and Implementation, 2023

2022
CAP-VMs: Capability-Based Isolation and Sharing for Microservices.
CoRR, 2022

CAP-VMs: Capability-Based Isolation and Sharing in the Cloud.
Proceedings of the 16th USENIX Symposium on Operating Systems Design and Implementation, 2022

Reconsidering OS memory optimizations in the presence of disaggregated memory.
Proceedings of the ISMM '22: ACM SIGPLAN International Symposium on Memory Management, 2022

Slashing the disaggregation tax in heterogeneous data centers with FractOS.
Proceedings of the EuroSys '22: Seventeenth European Conference on Computer Systems, Rennes, France, April 5, 2022

2021
Spons & Shields: practical isolation for trusted execution.
Proceedings of the VEE '21: 17th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2021

CubicleOS: a library OS with software componentisation for practical isolation.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2019
Using SMT to accelerate nested virtualization.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018
DATS - Data Containers for Web Applications.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Direct Inter-Process Communication (dIPC): Repurposing the CODOMs Architecture to Accelerate IPC.
Proceedings of the Twelfth European Conference on Computer Systems, 2017

2016
Code-Centric Domain Isolation: a hardware/software co-design for efficient program isolation.
PhD thesis, 2016

2015
Hardware-Software Coherence Protocol for the Coexistence of Caches and Local Memories.
IEEE Trans. Computers, 2015

Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Automatic Parallelization of Kernels in Shared-Memory Multi-GPU Nodes.
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

2014
CODOMs: Protecting software with Code-centric memory Domains.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Automatic execution of single-GPU computations across multiple GPUs.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
The low power architecture approach towards exascale computing.
J. Comput. Sci., 2013

Comparison based sorting for systems with multiple GPUs.
Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units, 2013

2011
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2009
Predictive Runtime Code Scheduling for Heterogeneous Architectures.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009


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