Liyi Xiao

Alfonso Sánchez-Macián

Juan Antonio Maestro

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019

A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs).

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Low Delay 3-Bit Burst Error Correction Codes.

[BibT_eX]

[DOI]

Jiaqiang Li

J. Electron. Test., 2019

Learning Reinforced Attentional Representation for End-to-End Visual Tracking.

[BibT_eX]

[DOI]

CoRR, 2019

Siamese Attentional Keypoint Network for High Performance Visual Tracking.

[BibT_eX]

[DOI]

CoRR, 2019

Single-event upset prediction in static random access memory cell account for parameter variations.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2019

Efficient Concurrent Error Detection for SEC-DAEC Encoders.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Learning Cascaded Siamese Networks for High Performance Visual Tracking.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2019

Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Efficient Implementations of 4-Bit Burst Error Correction for Memories.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A fast fault injection platform of multiple SEUs for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

High performance visual tracking with circular and structural operators.

[BibT_eX]

[DOI]

Knowl. Based Syst., 2018

Adaptive Object Tracking with Complementary Models.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2018

A Complementary Tracking Model with Multiple Features.

[BibT_eX]

[DOI]

CoRR, 2018

Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Large Margin Structured Convolution Operator for Thermal Infrared Object Tracking.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Pattern Recognition, 2018

2017

Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes.

[BibT_eX]

[DOI]

Alfonso Sánchez-Macián

Juan Antonio Maestro

IEEE Trans. Reliab., 2017

A method to recover critical bits under a double error in SEC-DED protected memories.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2017

Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016).

[BibT_eX]

[DOI]

Alfonso Sánchez-Macián

Juan Antonio Maestro

Microelectron. Reliab., 2017

A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Low redundancy matrix-based codes for adjacent error correction with parity sharing.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A fast and accurate fault injection platform for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Rongsheng Zhang

Jie Li

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Low-cost resilient radiation hardened flip-flop design.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A method to estimate cross-section of circuits at RTL levels.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Extend orthogonal Latin square codes for 32-bit data protection in memory applications.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

2015

Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2015

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2015

Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Novel technique for P-hit single-event transient mitigation using enhance dummy transistor.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Fault Secure Encoder and Decoder Designs for Matrix Codes.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

2014

Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology.

[BibT_eX]

[DOI]

Jing Guo

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation.

[BibT_eX]

[DOI]

Hai Huang

Microelectron. J., 2014

CORDIC-Based Unified Architectures for Computation of DCT/IDCT/DST/IDST.

[BibT_eX]

[DOI]

Hai Huang

Jiaming Liu

Circuits Syst. Signal Process., 2014

2013

CORDIC Based Fast Radix-2 DCT Algorithm.

[BibT_eX]

[DOI]

Hai Huang

IEEE Signal Process. Lett., 2013

Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs.

[BibT_eX]

[DOI]

IEEE Micro, 2013

A Low Power Built-in Self-Test Scheme Based on Overlapping Bit Swapping Linear Feedback Shift Register.

[BibT_eX]

[DOI]

J. Low Power Electron., 2013

2012

Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost.

[BibT_eX]

[DOI]

J. Low Power Electron., 2012

2011

New Mix codes for multiple bit upsets mitigation in fault-secure memories.

[BibT_eX]

[DOI]

Microelectron. J., 2011

Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping.

[BibT_eX]

[DOI]

J. Electron. Test., 2011

New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory.

[BibT_eX]

[DOI]

Ming Zhu

Hong Wei Luo

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

2010

DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current.

[BibT_eX]

[DOI]

Yu Sun

Cong Shi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in Memory.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008

A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata.

[BibT_eX]

[DOI]

Bei Cao

Yongsheng Wang

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Electronic Shelf Label System based on public illuminating network.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2003

A Test Architecture for System-on-a-Chip.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

A New Synchronization Algorithm for VHDL-AMS Simulation.

[BibT_eX]

[DOI]