Liyang Lai

According to our database, Liyang Lai authored at least 17 papers between 2004 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Parallel Static Learning Toward Heterogeneous Computing Architectures.

Xiaoze Lin, Liyang Lai, Huawei Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

Sideway Scan, Solving the Achilles' Heel of Scan-based Diagnosis.

Liyang Lai, Zefan Lin, Qitao Wang

Proceedings of the IEEE International Test Conference in Asia, 2024

2023

Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System.

Jingbo Hu, Guohao Dai, Liuzheng Wang, Liyang Lai, Yu Huang, Huazhong Yang, Yu Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

GPU-Based Concurrent Static Learning.

Huaxiao Liang, Xiaoze Lin, Liyang Lai, Naixing Wang, Yu Huang, Fei Yang, Yuxin Yang

Proceedings of the IEEE International Test Conference, 2023

2021

Scalable Parallel Static Learning.

Xiaoze Lin, Liyang Lai, Huawei Li

Proceedings of the IEEE International Test Conference in Asia, 2021

2020

GPGPU-Based ATPG System: Myth or Reality?

Liyang Lai, Kun-Han Tsai, Huawei Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

GPU-based Hybrid Parallel Logic Simulation for Scan Patterns.

Liyang Lai, Qiting Zhang, Kun-Han Hans Tsai, Wu-Tung Cheng

Proceedings of the IEEE International Test Conference in Asia, 2020

2015

Diagnosis and Layout Aware (DLA) Scan Chain Stitching.

Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan

IEEE Trans. Very Large Scale Integr. Syst., 2015

2009

STDF Memory Fail Datalog Standard.

Ajay Khoche, Jay Katz, Sauro Landini, Kochen Liao, Neetu Agrawal, Glenn Plowman, Songlin Zuo, Liyang Lai, John Rowe, Thomas Zanon

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008

Detection and Diagnosis of Static Scan Cell Internal Defect.

Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.

Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai

IEEE Des. Test Comput., 2007

Programmable Scan-Based Logic Built-In Self Test.

Liyang Lai, Wu-Tung Cheng, Thomas Rinderknecht

Proceedings of the 16th Asian Test Symposium, 2007

2006

Signature Based Diagnosis for Logic BIST.

Wu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

New Techniques for Logic Built -in Self -Test

Liyang Lai

PhD thesis, 2005

Hardware Ef.cient LBISTWith Complementary Weights.

Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004

Logic BIST Using Constrained Scan Cells.

Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Logic BIST with Scan Chain Segmentation.

Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004