Lisa M. Guerra

According to our database, Lisa M. Guerra authored at least 19 papers between 1992 and 2000.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2000

Cut-based functional debugging for programmable systems-on-chip.

Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra

IEEE Trans. Very Large Scale Integr. Syst., 2000

1999

Improving the observability and controllability of datapaths foremulation-based debugging.

Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Throughput optimization of general non-linear computations.

Inki Hong, Miodrag Potkonjak, Lisa M. Guerra

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification.

Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar, Chris Schläger, Bassam Tabbara, Vojin Zivojnovic

Proceedings of the 36th Conference on Design Automation, 1999

1998

Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's.

Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey

IEEE Trans. Very Large Scale Integr. Syst., 1998

Functional debugging of systems-on-chip.

Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

A Methodology for Guided Behavioral-Level Optimization.

Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey

Proceedings of the 35th Conference on Design Automation, 1998

1997

A partitioning scheme for optimizing interconnect power.

Renu Mehra, Lisa M. Guerra, Jan M. Rabaey

IEEE J. Solid State Circuits, 1997

1996

Low-power architectural synthesis and the impact of exploiting locality.

Renu Mehra, Lisa M. Guerra, Jan M. Rabaey

J. VLSI Signal Process., 1996

Permissible functions for multioutput components in combinational logic optimization.

Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Performance optimization using template mapping for datapath-intensive high-level synthesis.

Miguel R. Corazao, Marwan A. Khalaf, Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Design guidance in the power dimension.

Jan M. Rabaey, Lisa M. Guerra, Renu Mehra

Proceedings of the 1995 International Conference on Acoustics, 1995

1994

Concurrency characteristics in DSP programs.

Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey

Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

1993

Logic Optimization with Multi-Output Gates.

Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

High level synthesis for reconfigurable datapath structures.

Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Instruction set mapping for performance optimization.

Miguel R. Corazao, Marwan A. Khalaf, Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

High Level Synthesis Techniques for Efficient Built-In-Self Repair.

Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Heterogeneous BISR techniques for yield and reliability enhancement using high level synthesis transformations.

Miodrag Potkonjak, Lisa M. Guerra, Jan M. Rabaey

Proceedings of the International Conference on Application-Specific Array Processors, 1993

1992

An integrated system for rapid prototyping of high performance algorithm specific data paths.

D. C. Chen, Lisa M. Guerra, E. H. Ng, Miodrag Potkonjak, D. P. Schultz, Jan M. Rabaey

Proceedings of the Application Specific Array Processors, 1992