Liqiong Wei

According to our database, Liqiong Wei authored at least 21 papers between 1998 and 2019.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2019

A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique.

Liqiong Wei, Juan G. Alzate, Umut Arslan, Justin Brockman, Nilanjan Das, Kevin Fischer, Tahir Ghani, Oleg Golonzka, Patrick Hentges, Rawshan Jahan, Pulkit Jain, Blake C. Lin, Mesut Meterelliyoz, Jim O'Donnell, Conor Puls, Pedro A. Quintero, Tanaya Sahu, Meenakshi Sekhar, Ajay Vangapaty, Chris Wiegand, Fatih Hamzaoglu

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 3.6Mb 10.1Mb/mm² Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V.

Pulkit Jain, Umut Arslan, Meenakshi Sekhar, Blake C. Lin, Liqiong Wei, Tanaya Sahu, Juan Alzate-vinasco, Ajay Vangapaty, Mesut Meterelliyoz, Nathan Strutt, Albert B. Chen, Patrick Hentges, Pedro A. Quintero, Chris Connor, Oleg Golonzka, Kevin Fischer, Fatih Hamzaoglu

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2015

A 0.094um² high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist.

Kyung-Hoae Koo, Liqiong Wei, John Keane, Uddalak Bhattacharya, Eric A. Karl, Kevin Zhang

Proceedings of the Symposium on VLSI Circuits, 2015

2011

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design.

Fatih Hamzaoglu, Yih Wang, Pramod Kolar, Liqiong Wei, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang

IEEE Des. Test Comput., 2011

2010

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management.

Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr

IEEE J. Solid State Circuits, 2010

2009

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management.

Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.

Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr

IEEE J. Solid State Circuits, 2008

2007

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications.

Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Yih Zhang, Kevin Zhang, Mark Bohr

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2002

Vertically integrated SOI circuits for low-power and high-performance applications.

Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes

IEEE Trans. Very Large Scale Integr. Syst., 2002

IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions.

Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy

IEEE Des. Test Comput., 2002

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.

Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar

Proceedings of the 39th Design Automation Conference, 2002

2001

On effective I_DDQ testing of low-voltage CMOS circuits using leakage control techniques.

Zhanping Chen, Liqiong Wei, Kaushik Roy

IEEE Trans. Very Large Scale Integr. Syst., 2001

2000

Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs.

Liqiong Wei, Kaushik Roy, Vivek De

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.

Zhanping Chen, Liqiong Wei, Kaushik Roy

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness.

Naran Sirisantana, Liqiong Wei, Kaushik Roy

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Power minimization by simultaneous dual-V_th assignment and gate-sizing.

Liqiong Wei, Kaushik Roy, Cheng-Kok Koh

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999

Design and optimization of dual-threshold circuits for low-voltage low-power applications.

Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De

IEEE Trans. Very Large Scale Integr. Syst., 1999

Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.

Kaushik Roy, Liqiong Wei, Zhanping Chen

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Mixed-<i>V_th</i> (MVT) CMOS Circuit Design Methodology for Low Power Applications.

Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De

Proceedings of the 36th Conference on Design Automation, 1999

1998

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.

Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.

Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De

Proceedings of the 35th Conference on Design Automation, 1998