Lionel Torres
According to our database1,
Lionel Torres
authored at least 198 papers
between 1994 and 2024.
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Bibliography
2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024
2022
Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU Tandem.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Practical Experiments to Evaluate Quality Metrics of MRAM-Based Physical Unclonable Functions.
IEEE Access, 2020
Proceedings of the Cross Reality and Data Science in Engineering, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers.
IEEE Access, 2019
Practical Experiments on Fabricated TAS-MRAM Dies to Evaluate the Stochastic Behavior of Voltage-Controlled TRNGs.
IEEE Access, 2019
Proceedings of the IEEE Sensors Applications Symposium, 2019
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019
2018
A Ring Oscillator-Based Identification Mechanism Immune to Aging and External Working Conditions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Microelectron. J., 2018
J. Low Power Electron., 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Microprocess. Microsystems, 2017
Computing reliability: On the differences between software testing and software fault injection techniques.
Microprocess. Microsystems, 2017
SecBoot - lightweight secure boot mechanism for Linux-based embedded systems on FPGAs.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
IEEE Trans. Emerg. Top. Comput., 2016
Microprocess. Microsystems, 2016
STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability.
ACM J. Emerg. Technol. Comput. Syst., 2016
ACM J. Emerg. Technol. Comput. Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 11th European Workshop on Microelectronics Education, 2016
2015
Microprocess. Microsystems, 2015
J. Cryptogr. Eng., 2015
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
Proceedings of the Nordic Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Microelectron. Reliab., 2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs.
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Using electromagnetic emanations for variability characterization in Flash-based FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Trends on the application of emerging nonvolatile memory to processors and programmable devices.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Practical Analysis of RSA Countermeasures Against Side-Channel Electromagnetic Attacks.
Proceedings of the Smart Card Research and Advanced Applications, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
PI and PID Regulation Approaches for Performance-Constrained Adaptive Multiprocessor System-on-Chip.
IEEE Embed. Syst. Lett., 2011
IEEE Des. Test Comput., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011
2010
ACM Trans. Reconfigurable Technol. Syst., 2010
Block-Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor-Memory Transactions.
Trans. Comput. Sci., 2010
J. Low Power Electron., 2010
Selected Papers from ReconFig 2009 International Conference on Reconfigurable Computing and FPGAs (ReconFig 2009).
Int. J. Reconfigurable Comput., 2010
Int. J. Embed. Syst., 2010
Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories.
IET Comput. Digit. Tech., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Investigation of Digital Sensors for Variability Characterization on FPGAs.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM).
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Secure Protocol Implementation for Remote Bitstream Update Preventing Replay Attacks on FPGA.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
A Dynamic Reconfigurable MRAM based FPGA.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
Hardware Mechanisms for Memory Authentication: A Survey of Existing Techniques and Engines.
Trans. Comput. Sci., 2009
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Int. J. Reconfigurable Comput., 2008
Int. J. Reconfigurable Comput., 2008
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Convergence analysis of run-time distributed optimization on adaptive systems using game theory.
Proceedings of the FPL 2008, 2008
Proceedings of the FPL 2008, 2008
Proceedings of the FPL 2008, 2008
Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories.
Proceedings of the 13th European Test Symposium, 2008
2007
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
HS Scale: A run-time adaptable MP-SoC architecture.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007
2006
How to Secure Embedded Programmable Gate Arrays?
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Flexible security and its technology limits.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Remanent SRAM Structure for Runtime Reconfigurable FPGA.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
A Parallel and Secure Architecture for Asymmetric Cryptography.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the International Symposium on System-on-Chip, 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
A parallelized way to provide data encryption and integrity checking on a processor-memory bus.
Proceedings of the 43rd Design Automation Conference, 2006
Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2005
Méthode de caractérisation des architectures d'accélérateurs flexibles pour systèmes sur puce.
Tech. Sci. Informatiques, 2005
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Integration of Reconfigurable Logic on Secure Circuits.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
A new hardware countermeasure for masking power signatures of crypto cores.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Non-volatile SRAM-FPGA based on magnetic tunnelling junction.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
Proceedings of the 2005 Design, 2005
2004
Comput. Artif. Intell., 2004
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability.
Proceedings of the Computer Systems: Architectures, 2004
2003
Are coarse grain reconfigurable architectures suitable for cryptography?
Proceedings of the IFIP VLSI-SoC 2003, 2003
Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
2002
Iris recognition system for person identification.
Proceedings of the Pattern Recognition in Information Systems, 2002
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications.
Proceedings of the 2002 Design, 2002
2001
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001
Dynamically Reconfigurable Architectures for Digital Signal Processing Applications.
Proceedings of the SOC Design Methodologies, 2001
Proceedings of the Field-Programmable Logic and Applications, 2001
Proceedings of 8th IEEE International Conference on Emerging Technologies and Factory Automation, 2001
2000
Design of a Classification System for Rectangular Shapes Using a Co-Design Environment.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 2000 International Conference on Image Processing, 2000
1999
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999
Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies.
Proceedings of the VLSI: Systems on a Chip, 1999
Implementation of a Wavelet Transform Architecture for Image Processing.
Proceedings of the VLSI: Systems on a Chip, 1999
1998
Real Time Imaging, 1998
1996
Proceedings of the Field-Programmable Logic, 1996
1994
Proceedings of the Field-Programmable Logic, 1994