Lionel Bening

According to our database1, Lionel Bening authored at least 6 papers between 1979 and 2001.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2001
Optimizing Multiple EDA Tools within the ASIC Design Flow.
IEEE Des. Test Comput., 2001

Principles of verifiable RTL design - a functional coding style supporting verification processes in Verilog.
Kluwer, ISBN: 978-0-7923-7368-1, 2001

1999
A Two-State Methodology for RTL Logic Simulation.
Proceedings of the 36th Conference on Design Automation, 1999

1989
Critical path issue in VLSI design.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1982
Developments in logic network path delay analysis.
Proceedings of the 19th Design Automation Conference, 1982

1979
Developments in computer simulation of gate level physical logic.
Proceedings of the 16th Design Automation Conference, 1979


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