Lingli Wang

Orcid: 0000-0002-0579-3527

According to our database1, Lingli Wang authored at least 165 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Recognizing good variational quantum circuits with Monte Carlo Tree Search.
Quantum Mach. Intell., December, 2024

FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024

HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space Exploration.
ACM Trans. Reconfigurable Technol. Syst., June, 2024

HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024

FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism.
ACM Trans. Reconfigurable Technol. Syst., March, 2024

An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis.
ACM Trans. Design Autom. Electr. Syst., March, 2024

When the Clock Strikes: A Multimethod Investigation of On-the-Hour Effects in Online Learning.
Inf. Syst. Res., 2024

An Open-source End-to-End Logic Optimization Framework for Large-scale Boolean Network with Reinforcement Learning.
CoRR, 2024

An Architecture-Agnostic Dataflow Mapping Framework on CGRA.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

TransMap: An Efficient CGRA Mapping Framework via Transformer and Deep Reinforcement Learning.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

A CGRA Front-end Compiler Enabling Extraction of General Control and Dedicated Operators.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

MDCRA: A Reconfigurable Accelerator Framework for Multiple Dataflow Lanes.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

An End-to-End Agile Design Framework to Improve Energy Efficiency on CGRAs.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023
Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer.
IEEE Trans. Very Large Scale Integr. Syst., May, 2023

An Optimized GIB Routing Architecture with Bent Wires for FPGA.
ACM Trans. Reconfigurable Technol. Syst., March, 2023

First Things First? Order Effects in Online Product Recommender Systems.
ACM Trans. Comput. Hum. Interact., February, 2023

AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian Optimization.
CoRR, 2023

THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Dynamics and Impacts of Human-Algorithm Consensus in Logistics Scheduling: Evidence from A Field Experiment.
Proceedings of the 44th International Conference on Information Systems, 2023

A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications.
Proceedings of the International Conference on Field Programmable Technology, 2023

DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions.
Proceedings of the International Conference on Field Programmable Technology, 2023

Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs.
Proceedings of the International Conference on Field Programmable Technology, 2023

VIB: A Versatile Interconnection Block for FPGA Routing Architecture.
Proceedings of the International Conference on Field Programmable Technology, 2023

AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian Optimization.
Proceedings of the International Conference on Field Programmable Technology, 2023

AUGER: A Multi-Objective Design Space Exploration Framework for CGRAs.
Proceedings of the International Conference on Field Programmable Technology, 2023

GRAFT: GNN-based Adaptive Framework for Efficient CGRA Mapping.
Proceedings of the International Conference on Field Programmable Technology, 2023

HGBO-DSE: Hierarchical GNN and Bayesian Optimization based HLS Design Space Exploration.
Proceedings of the International Conference on Field Programmable Technology, 2023

E<sup>2</sup>-ACE: An Energy-Efficient Reconfigurable Crypto-Accelerator with Agile End-to-End Toolchain.
Proceedings of the International Conference on Field Programmable Technology, 2023

PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Multi-view Inverse Rendering for Large-scale Real-world Indoor Scenes.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

Rabbit: An Efficient Verification Platform Base on Virtual Peripherals.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

An Enhanced Packing Algorithm for FPGA Architectures without Local Crossbar.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

Permutation-Based Approximate Multiplier with High Accuracy.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

An Automatic Optimization Method of Combinational Logic Loops in CGRA.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

The Role of AI Assistants in Online Shopping Platforms: Evidence from Livestream Selling.
Proceedings of the 29th Americas Conference on Information Systems, 2023

2022
Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Acceleration of Rotated Object Detection on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A High-Performance and Scalable NVMe Controller Featuring Hardware Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Port-based supply chain decisions considering governmental pollution tax.
Oper. Res., 2022

Exploring Appropriate Communication Styles for Personalized Chatbots in Service Recovery.
Proceedings of the 26th Pacific Asia Conference on Information Systems, 2022

HEAM: High-Efficiency Approximate Multiplier optimization for Deep Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Efficient Reinforcement Learning Framework for Automated Logic Synthesis Exploration.
Proceedings of the International Conference on Field-Programmable Technology, 2022

GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

PhyIR: Physics-based Inverse Rendering for Panoramic Indoor Images.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

2021
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 2021

MRI-based brain tumor segmentation using FPGA-accelerated neural network.
BMC Bioinform., 2021

Heuristic Search for Activation Functions of Neural Networks Based on Gaussian Processes.
Proceedings of the International Joint Conference on Neural Networks, 2021

Effectiveness of AI Assistance in Live Streaming: A Randomized Field Experiment.
Proceedings of the 42nd International Conference on Information Systems, 2021

The Sales Data Sells: Effects of Real-Time Sales Analytics on Live Streaming Selling.
Proceedings of the 42nd International Conference on Information Systems, 2021

FastCGRA: A Modeling, Evaluation, and Exploration Platform for Large-Scale Coarse-Grained Reconfigurable Arrays.
Proceedings of the International Conference on Field-Programmable Technology, 2021

Parallelized Technology Mapping to General PLBs by Adaptive Circuit Partitioning.
Proceedings of the International Conference on Field-Programmable Technology, 2021

A Hexagon-Based Honeycomb Routing Architecture for FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2021

General routing architecture modelling and exploration for modern FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2021

LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2021

A High-Precision Flexible Symmetry-Aware Architecture for Element-Wise Activation Functions.
Proceedings of the International Conference on Field-Programmable Technology, 2021

APIR-DSP: An approximate PIR-DSP architecture for error-tolerant applications.
Proceedings of the International Conference on Field-Programmable Technology, 2021

Two-level MUX Design and Exploration in FPGA Routing Architecture.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

A High-performance Open-channel Open-way NAND Flash Controller Architecture.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA.
IEEE Trans. Parallel Distributed Syst., 2020

Fast Exact NPN Classification by Co-Designing Canonical Form and Its Computation Algorithm.
IEEE Trans. Computers, 2020

Achieving Flexible, Low-Latency and 100Gbps Line-rate Load Balancing over Ethernet on FPGA.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Effects of Voice-Based AI in Customer Service: Evidence from a Natural Experiment.
Proceedings of the 41st International Conference on Information Systems, 2020

GIB: A Novel Unidirectional Interconnection Architecture for FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2020

High Throughput and Low Latency Multi-Version Management Key-Value Storage Accelerator.
Proceedings of the International Conference on Field-Programmable Technology, 2020

A Low-Cost Reconfigurable Nonlinear Core for Embedded DNN Applications.
Proceedings of the International Conference on Field-Programmable Technology, 2020

LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019
Fast Adjustable NPN Classification Using Generalized Symmetries.
ACM Trans. Reconfigurable Technol. Syst., 2019

ARBSA: Adaptive Range-Based Simulated Annealing for FPGA Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks.
IEICE Trans. Inf. Syst., 2019

A snapback-free RC-LIGBT with separated LDMOS and LIGBT by the L-shaped SiO<sub>2</sub> layer.
IEICE Electron. Express, 2019

Targeted Black-Box Adversarial Attack Method for Image Classification Models.
Proceedings of the International Joint Conference on Neural Networks, 2019

A Complete CPU-FPGA Architecture for Protein Identification with Tandem Mass Spectrometry.
Proceedings of the International Conference on Field-Programmable Technology, 2019

High-Throughput and Low-Latency Distributed Management Proxy for Key-Value Store Over 100Gbps Ethernet on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2019

SpWMM: A High-Performance Sparse-Winograd Matrix-Matrix Multiplication Accelerator for CNNs.
Proceedings of the International Conference on Field-Programmable Technology, 2019

MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency.
Proceedings of the International Conference on Field-Programmable Technology, 2019

A High Performance FPGA-Based Accelerator Design for End-to-End Speaker Recognition System.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Bent Routing Pattern for FPGA.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A Low-Latency Multi-Version Key-Value Store Using B-Tree on an FPGA-CPU Platform.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
Stream Processing Dual-Track CGRA for Object Inference.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Ultra-Low Latency and High Throughput Key-Value Store Systems Over Ethernet.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

The "On-the-Hour Effect": How Do Users Allocate Time to Different Modules in e-Learning Apps?
Proceedings of the International Conference on Information Systems, 2018

High Throughput CNN Accelerator Design Based on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Ultra-Low-Latency and Flexible In-memory Key-Value Store System Design on CPU-FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Fast Adjustable NPN Classification using Generalized Symmetries.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A Novel Low-Communication Energy-Efficient Reconfigurable CNN Acceleration Architecture.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
5G MIMO Conformal Microstrip Antenna Design.
Wirel. Commun. Mob. Comput., 2017

Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Estimation of Surface Soil Moisture in Cornfields Using a Modified MODIS-Based Index and Considering Corn Growth Stages.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2017

A quantum-implementable neural network model.
Quantum Inf. Process., 2017

基于MEAN+SpringMVC的服务管理平台的设计与实现 (Design and Implementation of Service Management Platform Based on MEAN and SpringMVC).
计算机科学, 2017

基于NodeJS +Express框架的轻应用定制平台的设计与实现 (Design and Implementation of Light Application Customizations Platform Based on NodeJS and Express Framework).
计算机科学, 2017

RBSA: Range-based simulated annealing for FPGA placement.
Proceedings of the International Conference on Field Programmable Technology, 2017

A scalable hybrid architecture for high performance data-parallel applications.
Proceedings of the International Conference on Field Programmable Technology, 2017

FPGA acceleration of the scoring process of X!TANDEM for protein identification.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Accelerating low bit-width convolutional neural networks with embedded FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

A high performance real-time edge detection system with NEON.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Parallel sparse LU decomposition using FPGA with an efficient cache architecture.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Analytical models for channel potential, threshold voltage, and subthreshold swing of junctionless triple-gate FinFETs.
Microelectron. J., 2016

E-WOM from e-commerce websites and social media: Which will consumers adopt?
Electron. Commer. Res. Appl., 2016

Study on the influencing factors of unplanned consumption in a large online promotion activity.
Electron. Commer. Res., 2016

High-performance K-means Implementation based on a Coarse-grained Map-Reduce Architecture.
CoRR, 2016

An improved measurement method of large hot forgings based on laser-aided multi-view stereo vision.
Proceedings of the 25th IEEE International Symposium on Industrial Electronics, 2016

High performance Deformable Part Model accelerator based on FPGA.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A moving object extraction and classification system based on Zynq and IBM SuperVessel.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Memory efficient and high performance key-value store on FPGA using Cuckoo hashing.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

A high performance FPGA-based accelerator for large-scale convolutional neural networks.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
An adaptive cross-layer fault recovery solution for reconfigurable SoCs.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

UniStream: A unified stream architecture combining configuration and data processing.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Implementation of high performance hardware architecture of face recognition algorithm based on local binary pattern on FPGA.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

An automated test framework for SRAM-based FPGA.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Analytical models for threshold voltage, drain induced barrier lowering effect of junctionless triple-gate FinFETs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Design space exploration for FPGA-based hybrid multicore architecture.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

No zero padded sparse matrix-vector multiplication on FPGAs.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Fast Filter-Based Boolean Matchers.
IEEE Embed. Syst. Lett., 2013

A hardware implementation of Bag of Words and Simhash for image recognition.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

An FPGA-cluster-accelerated match engine for content-based image retrieval.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Fast Boolean matching based on NPN classification.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Quantum FPGA architecture design.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

An auscultatory technique of Chinese medicine: Pattern recognition based on timbre of human-voice matching with standardized patterns of sound from Bianzhong of Marquis Yi of Zeng (***).
Proceedings of the 2013 IEEE International Conference on Bioinformatics and Biomedicine, 2013

Analytic models for electric potential and subthreshold swing of the dual-material double-gate MOSFET.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A reconfigurable floating-point FFT architecture.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments.
IEEE Trans. Very Large Scale Integr. Syst., 2012

General Parameterized Thermal Modeling for High-Performance Microprocessor Design.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Changing-Weight Filter Method for Reconstructing a High-Quality NDVI Time Series to Preserve the Integrity of Vegetation Phenology.
IEEE Trans. Geosci. Remote. Sens., 2012

Quantum mechanical effects on the threshold voltage of surrounding-gate MOSFETs.
Microelectron. J., 2012

Evaluation of phenology extracting methods from vegetation index time series.
Proceedings of the 2012 IEEE International Geoscience and Remote Sensing Symposium, 2012

Evaluation of similarity measure methods for hyperspectral remote sensing data.
Proceedings of the 2012 IEEE International Geoscience and Remote Sensing Symposium, 2012

A phenology-preserving filtering method to reduce noise in NDVI time series.
Proceedings of the 2012 IEEE International Geoscience and Remote Sensing Symposium, 2012

Lazy man's logic synthesis.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

A partially reconfigurable architecture supporting hardware threads.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

An analytic model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs.
Microelectron. J., 2011

The model of high-order multidimensional tree with tristate applied to the digitalization of Yin-Yang theory of Traditional Chinese Medicine.
Proceedings of the 2011 IEEE International Conference on Bioinformatics and Biomedicine Workshops, 2011

A method to build reconfigurable architectures by extracting common subgraphs.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Automatic layout generator for embedded FPGA cores.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A coarse-grained reconfigurable computing unit.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A permutation network for configurable and scalable FFT processors.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Accelerating Boolean Matching Using Bloom Filter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Engineering a scalable Boolean matching based on EDA SaaS 2.0.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Cropland parcels extraction based on texture analysis and multi-spectral image classification.
Proceedings of the 18th International Conference on Geoinformatics: GIScience in Change, 2010

General switch box modeling and optimization for FPGA routing architectures.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Building a faster boolean matcher using bloom filter.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2008
MODIS On-Orbit Spatial Characterization Using Ground Targets.
IEEE Trans. Geosci. Remote. Sens., 2008

Techniques for dual forms of Reed-Muller expansion conversion.
Integr., 2008

2006
A new method for retrieving band 6 of aqua MODIS.
IEEE Geosci. Remote. Sens. Lett., 2006

Asian Dust Storm Monitoring Combining Terra and Aqua MODIS SRB Measurements.
IEEE Geosci. Remote. Sens. Lett., 2006

Analysis on the Drawbacks of the Commonly Used Measures of the Significance of Attributes in Decision-Table & A New Measure.
Proceedings of the Interdisciplinary and Multidisciplinary Research in Computer Science, 2006

Fast Conversion for Large Canonical OR-Coincidence Functions.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Study of african dust storm and its effects on tropical cyclones over Atlantic Ocean from space.
Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2005

Development and enhancement of calibration/validation toolkit for supporting NPOESS/NPP missions.
Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2005

2001
Multilevel Logic Minimization Using Functional Don't Cares.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001


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