Linda E. M. Brackenbury

According to our database, Linda E. M. Brackenbury authored at least 12 papers between 1999 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

System-on-Chip Design and Implementation.

Linda E. M. Brackenbury, Luis A. Plana, Jeffrey Pepper

IEEE Trans. Educ., 2010

Early stopping turbo decoders: a high-throughput, low-energy bit-level approach and implementation.

Wei Shao, Linda E. M. Brackenbury

IET Commun., 2010

2008

Pre-processing of convolutional codes for reducing decoding power consumption.

Wei Shao, Linda E. M. Brackenbury

Proceedings of the IEEE International Conference on Acoustics, 2008

2007

Lowering power in an experimental RISC processor.

Linda E. M. Brackenbury, Wei Shao

Microprocess. Microsystems, 2007

No-Handshake Asynchronous Survivor Memory Unit for a Viterbi Decoder.

Wei Shao, Linda E. M. Brackenbury

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2004

An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm.

Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury

Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2002

CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications.

Mike J. G. Lewis, Linda E. M. Brackenbury

Des. Autom. Embed. Syst., 2002

2001

CADRE: A Low-power, Low-EMI DSP Architecture for Digital Mobile Phones.

Mike J. G. Lewis, Linda E. M. Brackenbury

VLSI Design, 2001

A Low-Power Self-Timed Viterbi Decoder.

Peter A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber

Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank.

Mike J. G. Lewis, L. E. M. Brackenbury

Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

2000

An Instruction Buffer for a Low-Power DSP.

Mike J. G. Lewis, L. E. M. Brackenbury

Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999

Reconfigurable Latch Controllers for Low Power Asynchronous Circuits.

Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury

Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999